TCL for Modelsim
Rob Keiber
I am looking for some kind of tutorial of how to use TCL with Modelsim.
Basically I wanna use it to set some signals & buses to some values in
a loop and read out the result. Anyone could give me a bit help in this
matter, in google looking for TCL & Modelsim just gives me always links
to pdf files that Modelsim supports TCL...
THanks
Uwe Klein
These may help ( all via google "modelsim+tcl+scripting" ):
http://www.altera.com/support/examples/tcl/tcl-modelsim.html
http://www.cs.bris.ac.uk/Teaching/Resources/COMSM0115/ModelSimTutorial/modelsim_se_5_7_quick_ref.pdf
http://www.model.com/support/technotes/tcl_tk/tcl_testbench.pdf
http://en.wikibooks.org/wiki/TCL_SCRIPT_FOR_MODELSIM_USERS
uwe
Rob Keiber
> These may help ( all via google "modelsim+tcl+scripting" ):
> http://www.altera.com/support/examples/tcl/tcl-modelsim.html
> http://www.cs.bris.ac.uk/Teaching/Resources/COMSM0115/ModelSimTutorial/modelsim_se_5_7_quick_ref.pdf
>
> http://www.model.com/support/technotes/tcl_tk/tcl_testbench.pdf
> http://en.wikibooks.org/wiki/TCL_SCRIPT_FOR_MODELSIM_USERS
>
> uwe
Thanks Uwe, I just came also across some of these ressources (looking
modelsim & tcl testbench ;). Anyway, it gives more information about how
to scripts that allow compilation etc, a more detailed description of
how to set some input for a signal would be helpful.
Cheers,
Rob
Rob Keiber
> Thanks Uwe, I just came also across some of these ressources (looking
> modelsim & tcl testbench ;). Anyway, it gives more information about how
> to scripts that allow compilation etc, a more detailed description of
> how to set some input for a signal would be helpful.
I just tried a simple RESET script that should put me a high value on
the rst pin for some time and then release it and go back to ZERO. THis
looks then as follows.
proc TCL_reset {} {
global MC_CLK
#BIT0 presetn
set /testbench/rst 1
run [expr 10 * $MC_CLK] ns
#BIT1 presetn
set /testbench/rst 0
run 366 ns
}
However, when I check my wave forms then I just see an undefined value
for /testbench/rst... Anyone an idea how to write to this input value
of the testbench in VHDL?
Thanks Rob
Jonathan Bromley
>I just tried a simple RESET script that should put me a high value on
>the rst pin for some time and then release it and go back to ZERO. THis
>looks then as follows.
>
>proc TCL_reset {} {
> global MC_CLK
>
> #BIT0 presetn
> set /testbench/rst 1
>
>
> run [expr 10 * $MC_CLK] ns
>
> #BIT1 presetn
> set /testbench/rst 0
>
> run 366 ns
>}
>
>However, when I check my wave forms then I just see an undefined value
>for /testbench/rst...
That's because "set" is the Tcl command to set a Tcl variable.
What you want is the ModelSim command to force a VHDL signal
to a value - it's the "force" command, and it is very well
documented in ModelSim's help docs. Your code has created
an idiotically named Tcl variable /testbench/rst, whose
value you could only discover by using curly braces thus:
echo ${/testbench/rst}
(Note for regular Tclers: in the ModelSim digital simulator,
[puts] uses good ol' stdout, whereas most users expect to see
their output popping up in the ModelSim GUI's console; that's
what the [echo] command does)
> Anyone an idea how to write to this input value
Try replacing your [set] commands with [force].
Also, look up the [examine] command which allows you to inspect
the value of HDL signals.
And don't forget that ModelSim exposes a global variable
called "now" which contains the current simulated time.
Finally, try taking your questions to comp.lang.vhdl or
comp.arch.fpga, where there is likely to be a much higher
concentration of ModelSim Tclers (but, sadly, much less
expertise on Tcl in general) than you'll find here!
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan...@MYCOMPANY.com
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