rickman wrote:
> On 10/9/2012 7:11 PM, Bernd Paysan wrote:
>> For small designs, they are almost perfect now.  A coworker
>> asked me about a particular Verilog construct in the b16 ALU, and I
>> explained him how I build an ALU out of a full adder and two
>> multiplexer
>> per bit.  He said "the synthesis tool is never going to do that for
>> you", and I checked: It did.  Both the current synthesis tool from
>> Cadence and Synopsys did what I wanted them to do.

> What was the construct he said you couldn't get from synthesis, a mux
> on each input bit?  Why would that be hard to synthesize?  Also, what
> did this buy you?

> In my CPU design I wanted the address sequencer to be as fast as
> possible and I found I could use the incrementer/adder as a mux as
> well.
>   So that logic all fit in one 4-input LUT.  I think I had the
> instruction fetch loop down to the decode logic plus two levels of
> LUTs
> and the memory setup and hold time.  Turned out it was the stack
> address
> units that slowed the design the most, the error flags actually.  Good
> reason to toss the flags I suppose.