From: Bernd Paysan <bernd.pay...@gmx.de>
Date: Wed, 10 Oct 2012 14:48:19 +0200
Local: Wed, Oct 10 2012 8:48 am
Subject: Re: Your next supercomputer! Just $99 for 16 ARM cores on a chip. (link supplied)
rickman wrote:I think he was more sceptical about the full adder. This is very
> On 10/9/2012 7:11 PM, Bernd Paysan wrote:
>> For small designs, they are almost perfect now. A coworker
>> asked me about a particular Verilog construct in the b16 ALU, and I
>> explained him how I build an ALU out of a full adder and two
>> per bit. He said "the synthesis tool is never going to do that for
>> you", and I checked: It did. Both the current synthesis tool from
>> Cadence and Synopsys did what I wanted them to do.
> What was the construct he said you couldn't get from synthesis, a mux
compact and buys space. The guy also argued that space isn't an issue
at all at 180nm, and therefore could be wasted, and my reply was "that's
why your part is huge and mine is small".
> In my CPU design I wanted the address sequencer to be as fast asAccording to my ex-coworker, you should not try to optimize the design
> possible and I found I could use the incrementer/adder as a mux as
> So that logic all fit in one 4-input LUT. I think I had the
> instruction fetch loop down to the decode logic plus two levels of
> and the memory setup and hold time. Turned out it was the stack
> units that slowed the design the most, the error flags actually. Good
> reason to toss the flags I suppose.
for speed or area, but rather for readability by idiots. Because as
they are mean to you, you will quit, and then these idiots will have to
maintain your code. Any sort of cleverness is strictly prohibited.
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