Received: by 10.204.149.65 with SMTP id s1mr876343bkv.3.1350352603124;
        Mon, 15 Oct 2012 18:56:43 -0700 (PDT)
Path: q11ni134324904wiw.1!nntp.google.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!94.232.116.11.MISMATCH!feed.xsnews.nl!border-1.ams.xsnews.nl!border3.nntp.ams.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!news.panservice.it!feeder.erje.net!news-1.dfn.de!news.dfn.de!npeer.de.kpn-eurorings.net!npeer-ng0.de.kpn-eurorings.net!feed.news.schlund.de!schlund.de!news.online.de!not-for-mail
From: Bernd Paysan <bernd.pay...@gmx.de>
Newsgroups: comp.lang.forth
Subject: Re: Your next supercomputer! Just $99 for 16 ARM cores on a chip. (link supplied)
Date: Wed, 10 Oct 2012 01:11:42 +0200
Organization: 1&1 Internet AG
Lines: 38
Message-ID: <8655639.6yfpS9rpgy@sunwukong.fritz.box>
References: <76fe0697-97b3-4844-9b18-b2b86e028d8c@googlegroups.com> <971ca4fc-0ec5-457b-b941-c268c2cc48fe@z8g2000yql.googlegroups.com> <2012100820430026080-chrishinsley@gmailcom> <k4vbco$v5m$1@dont-email.me> <50748947$0$51970$c3e8da3$c8b7d2e6@news.astraweb.com> <k523uj$jk8$1@dont-email.me>
NNTP-Posting-Host: p5dcd61fe.dip0.t-ipconnect.de
Mime-Version: 1.0
X-Trace: online.de 1349824302 3170 93.205.97.254 (9 Oct 2012 23:11:42 GMT)
X-Complaints-To: abuse@einsundeins.com
NNTP-Posting-Date: Tue, 9 Oct 2012 23:11:42 +0000 (UTC)
User-Agent: KNode/4.8.5
Bytes: 3269
Content-Type: text/plain; charset="ISO-8859-1"
Content-Transfer-Encoding: 7Bit

rickman wrote:
> I shouldn't speak for the chip designers, but from what they have
> written, they could ONLY design this chip using their own tools.  They
> even talk about how SPICE is broken and should not be used for
> anything because it did not accurately model their designs.

Yes, I've heard that, too.  I've done simulations with the same process 
(180nm TSMC logic process), and Spice/Spectre was perfectly right and 
accurate.  TSMC's models have a rather good reputation, most of the time 
accurate to the point (though some model parameters like resistor tempco 
are only available under typical conditions).  I don't know what Chuck 
did wrong, but I think he did something wrong.  I had tutored a few 
beginners, and you can indeed make quite a number of mistakes with these 
tools.

Chuck doesn't like these complex and horribly expensive tools, but if 
you negotiate, these tools are far less expensive than wasting years 
with full-custom hand-layout, they do get a lot of work done for you.  
As this is mostly a digital chip, I wouldn't even consider using Spice, 
the digital models are accurate enough.  Chucks horror storries about 
conventional tools go pretty far back in time, at least back to ShBoom.  
That's more than 20 years.  Yes, the tools were really bad back then.

The tools have gotten better over time.  I had been pretty annoyed by 
the tools nearly 15 years ago, when I started.  They often didn't do 
what I wanted them to do, or at least were suboptimal.  But they 
improved.  For small designs, they are almost perfect now.  A coworker 
asked me about a particular Verilog construct in the b16 ALU, and I 
explained him how I build an ALU out of a full adder and two multiplexer 
per bit.  He said "the synthesis tool is never going to do that for 
you", and I checked: It did.  Both the current synthesis tool from 
Cadence and Synopsys did what I wanted them to do.

-- 
Bernd Paysan
"If you want it done right, you have to do it yourself"
http://bernd-paysan.de/