Re: ANSI FORTH: The Penultimate Universal Language Translator Solution . . .
Reply74...@wmconnect.com
And The Dynamic Unbound Universal Turing Machine
( start of article )
. . .
... In summation, Fully extended ANSI FORTH, as defined, is a simple
interpretive parser and merely suggests a ( native) bytecode
compilation.
As for language translation for supervisory control, the most accurate
technique available is a hybrid architecture of Consequentiality (
current state of events) and Neccessity ( desired events). All objects
MUST be bound with NIL ( traditional /nothingness/) by some fuzzy
duality equation ( Consequentiality and Necessity) , All Class Objects
Are ( Mostly) Not Nil. All non-NIL Objects, other than *address-zero*
equate, use memory. Any Object equated with NIL is immediately marked
as free memory.
---
Copyright 2005,
Washburn,
ALL RIGHTS RESERVED.
---
'Unbounded' is not a word in my dictionary.
Reply74...@wmconnect.com
Example ( MISC) primitives set,
ANSI explicit:
0< SWAP AND XOR DROP OVER DUP @ ! 2* 2/ >R R> INVERT +
ANSI implicit:
JUMP_IF_ZERO
JUMP
CALL
RETURN
LITERAL
---
Example extended on-chip stack register map,
sixteen ( 16) return stack elements,
eight ( 8) parameter stack elements,
four ( 4) Supplementary stack elements ( X, Y),
thirty two ( 32) status /machine state logic/ stack elements
---
Example Dual-bus MIMD SMP map, ( Multiple Instruction Multiple Data,
Symmetric Multiple Processor,)
( Note, example 'extended on-chip stack register map'
applies to the sixteen by sixteen dual-bus diagonal ONLY. Other nodes
may boot their nodes from ROM with specific multiplexing of messaging,
for example a simplified, ATM like protocol, ( loaded from ROM at boot
/reset,) might be specified for all of the non-diaganal, as well as,
the diagonal nodes, HOWEVER, the non-diagonal nodes may not require an
extended on-chip stack register map for simple bus to bus message
routing protocol, whereas, the diagonal features a C register (, as
well as, A and B) for the extended on-chip stack engine random access
memory ( RAM) exclusive buses, one C bus for each extended on-chip
stack register map, whew!))
URL,
http://groups.google.com/group/comp.lang.java.machine/msg/b400d03ddc0f5a4f?dmode=source&hl=en
---
Example 16-bit VLIW protocol
URL,
http://groups.google.com/group/comp.lang.java.programmer/msg/028ab82ac81f0014?dmode=source&hl=en
---
For a better design constraint of 1) maximum CPU fabrication efficiency
and chip logic compactness, together, 2) for maximizing circuit
utilization for data processing and digital signal processing
bandwidth.
regards,
mawcowboyusa
EarlCox
"anon...@netscape.net" <Reply74...@wmconnect.com> wrote in message
news:1127581933.5...@g47g2000cwa.googlegroups.com...
Why is this the second to the last universal language translator solution??
Ulrich Hobelmann
> Why is this the second to the last universal language translator solution??
Because the JVM exists ;)
SCNR
--
Do or do not. There is no try.
Yoda
Anton van Straaten
Perhaps the author wishes to avoid being immodest.
Anton
Reply74...@wmconnect.com
Sunday, October 2nd, Of This Christ's Year Two Thousand and Five,
9:31am,
Because ANSI FORTH is only a rough approximation of the 16-bit VLIW
protocol theory, where 85% of the fully compressed dynamic frequency
profile is bound.
( Within VLIW SMP MPP FORTH, the root chip model formula I have effort
to communicate to my good neighbors in Washington for about ten years
now. ( few have reciprocated my invitation for public discourse))
VLIW SMP MPP FORTH is derivative of an "ultimate" "holy grail" "grand
unification" extended stack machine architecture model theory implied
within a frame of fourty years of computerized arithmetic and human
history ( minus ten years of my history).
( However, I suspect you already are well familiar with stack machine
theory and my models)
regards,
maw
9:52am,18min,
Reply74...@wmconnect.com
For a clearer visualization of my/your formula ontology,
MPP, ( multiple parallel processors)
SMP, ( symmetric multiple processors)
FORTH, ( an interpretive stack machine language with a minimal
instruction set implied),
VLIW, ( an extended stack machine architecture, a fattened FORTH
from application profile testing ( and dozens of my best guesstimates
:) ))
regards,
maw
10:12,12min,
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