Minor Update:
I did some more research last night, and managed to find some good
things. I've made some good discoveries that fgiut in with what I wnt
to do as well.
What I am writing here is a condernsed summary resource of little
clear explanations, assessments, and some opinion, strung together.
A sentence might cover simply two or three related aspects. It also
builds on information in prior posts. So, please read it carefully
from the beginning of the thread to get a proper understanding. If
people want me to expand out each little explanation further, even
little cartoons like in Starting Forth, to understand it better, then
just this post might take up to a 100 posts to excplain. :-) The
resource links, context, and previous posts are there to read. The
thread is suitably short for professionals to read through it, and I
am summarising information in update posts like this, so all that is
really needed is to read the updates and the posts since the last
update. I might eventually start a new thread with a summary of the
summaries in the future for new people to easily get started.
Please, if you know anybody in Misc, ask them to come over now and
again and see if they want to contribute something to projects, or a
project. It is very much a matter of, developing effectively for misc
will develop more markets for misc. In this day and age, wireless
applications in particular will be a big thing, to have wireless.
Relative standards are listed in previous posts, in particular the
ieee basis for variouse ermbedded personal area networks. There is a
proposal for a network for smart dust too (around the size of a misc
array at 22nm process.
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It appears there are high speed serial onboard interconnect busses out
there for mobile supported by mipi, an Arm initiative, I don't know if
they are excternal busses yet, but from the slow speed and dervices, I
guess at least some of them are. If the is an open spec, and if it
has a good parts list, it would be good if GA had support for this eco
system. I'm surprised that nobody here knew of this system.
http://en.wikipedia.org/wiki/Mobile_Industry_Processor_Interface
http://www.mipi.org/
http://www.mipi.org/about-mipi/mipi-interfaces-mobile-platform
http://www.mipi.org/about-mipi/frequently-asked-questions
Slimbus, one of the busses basically goes at 28 MB/s, not too much
faster than 4 lane spi unfortunately, but is a two pin muli drop
serial bus, likely with dma as standard, which in spi, would have had
to be added through extra general purpose pins. So heart warming. If
it was 280MB/s instead of 28MB/s and could interface most things,I
would be much happier. :-) However, there are other buses, one with
300MB/s, and support for both mobile forms I think of pcie and USB 3,
however, detail and speed constrictions I don't know. There are many
busses.
http://en.wikipedia.org/wiki/Slimbus
http://www.mipi.org/content/mipi-alliance-rolls-out-slimbus®
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An ideal embeeded interconnect onboard devices bus.
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What I would like to see is a multi speed combined single and multiple
drop bus, with ultra simple point to point no protocol support (for
embedded naked io apps) and multiple optional protocol level
depending on hardware attached. The speed also would be dependent on
devices attached to the line, as with the voltage etc. In reality,
you just make your port fit a certain max speed and a voltage etc, and
choose parts that fit, and optionally making it multi voltage. So in
its simplest form you attach all devices of the same speed (even just
async for GA) to the same lines. If you have a high speed device that
you require a lower speed device with, you have coexistence protocol
support, or virtual hub support in the high speed and daisy chain the
slower speed device on it. All together, except for optional security
handling, encryption and data recovery options, you make the whole
driver protocol software fit in a few KB. Once a device is attached
either you know how it is handled and add the software, or it is sense
dynamically. You pick the highest speed serial bus practical, and
move onto higher speed buses again in future versions, with either
sensing/locking switchable coexistence for the pins, or new pins, and
pick parts to suit the new bus version standard used. In this way you
don't get stuck with trying to upgrade to a backwards compatible, and
likely limited from being compatible, bus protocol. Also imagine if
it was multiple phase, I dont know how sophisicated a circuit is
needed to do this (thinking of practicality on small chips like misc)
but imagine if you can resolve a 16 bit adress in a serial line in a
single pulse, ideal for small embedded, and two lines makes 32 bits
for large embedded. I notice that past Misc designs have large
internal speed overhead compared to the port or processor clock speed,
so maybe this can be simply used towards multi phase timing, even if
just 4 bits at a time, giving you four lines for four 16 bits, and 8
for 32 bit, meaning more memory busses for the same pin count. So you
can pick maybe pcie or thunderbolt to start, or hyper transport or
rapidio (what was the name of that Intel one again). However, one
mode would be custom protocol, that allows any data protocol to be
used on it, maybe with some support to ensure data integrity of the
electrical signalling. This means it is possible to use USB and
thunderbolt with as the seriasl line, maybe with a electrical bridging
chip and isolation built into the connector, straight off the board to
external services. So, now we have something that makes it not only
cheaply useable for small run use, but also for mass production, and
delivering 90% of the benefits of a very complex bus system. The same
could be done for wireless standards, having a common program
interface for multiple wireless standards.
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Now, I happened on mipi by accident, even though I spent a while
looking for newer busses on line. I found it after I looked up a new
memory bus technology, called serial port memory technology, using
spdram. Promised much, was a thing Arm was behind and from silicon
image who do HDMI, and wirelesshd that I mentioned. In that edition
it was only 6 GByte/s for a 4 port serial, and interesting, also aimed
at interconnect use. It gets a dram chip and serialises the data,
likely saving a few pins. The website is blank, I'm going to have to
try another browser, but apparently they did not get much acceptence
at first, as the industry was skeptical. So the next year they shook
up management and brought about a much faster version hybridised with
parallel, that is to be incorporated into the lpsdram interface. Now
20GBytes/s I think, 4 port serial. A number of the original members
left, including Intel, so it would be interesting to see what they
have planned as they plans to move thunderbolt to phones, but I'm very
interested in this one, imagine the peripheral use, I think you can
limit the number of ports, as well as the speed. If the protocol/
electrical is simple ernough, a natural for high performance ermbeeded
GA system in a faster process.
www.eetimes.com/electronics-news/4205016/Memory-interface-group-claims-to-be-back-on-track-
http://www.spmt.org/
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I also found a more modern Intel 4 bit version of the ISA bus, that
Intel introduced, I think up to 12 or so MB/s, but I don't know how
many parts would be left for it these days, and then mipi eco system
is better in speed and for mobile embedded.
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Now, here is some links on converting C++ to C programs. Apparently
that is how the inventor of c++ started out. It looks like Stephen's
c to forth solution is a rather elegant solution along the lines I was
theorising, well worth investegating. Pity that with everything I
want and have to do, it is not my sort of thing to investigate, but is
for others that are intetested. I list a few links on c to forth as
well.
http://www.parashift.com/c++-faq/convert-to-c.html
http://www.tomshardware.com/forum/236425-50-open-source-translation
http://sydney.edu.au/engineering/it/~scilect/tpop/handouts/CPP_to_C.htm
http://www.complang.tuwien.ac.at/forth/faq/faq-general-5.html
http://dl.acm.org/citation.cfm?id=316994
http://compilers.iecc.com/comparch/article/91-12-03
http://compilers.iecc.com/comparch/article/07-07-046
This might not be an acceptabe solution to everybody, but it is here
for those that want it.
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I see that there has been some talk about getting Java on Forth or
Misc, and have a few links about this.
http://computer-programming-forum.com/22-forth/d73ec2f837359b09.htm
http://www.complang.tuwien.ac.at/forth/faq/faq-general-5.html#ss5.7
Does anybody have infoirmatiom on implermrntatiins of this? I thought
people from the intellasys days tried something. Having a Java OS in
Java, would help reduce the hassel of moveing it over.
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I think I might be interested in working with somebody in future to
emulate an arm processor on Misc or translate code (with good
attitudes). I could certainly offer a lot of innovative ideas, to
greatly increase the speed of emulation. However the only ARM
assembly text here I have is from the Arm 1 or 3 series. I will have
to get a hang of both systems first, to maximise results. The on chip
eco system is probably the biggest issue, it is large and expansive.
Or maybe somebody would like to work on c on misc as an alternative,
and maybe ask to work with Stephen on his code (brawn and brains).
C, Arm and Java offer the best eco system expansion chioces (Arm and C
offer Android and Linux).
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The modern reality is that the industry has become a commodity like
market in order to make money. So we need a software and hardware eco
system for our own products to make impact on the commodity side. It
is too expensive to make our own eco systems of products, so we have
to tap into others to get to a point of being able to afford to make
our own, or wait for developers to make it. So, c, Java etc short
term is a desirable thing.
Thanks
Steve.