On 2/9/2016 12:13 PM, Geoff wrote:
> On Tue, 9 Feb 2016 08:33:41 -0500, Jerry Stuckle
> <
jstu...@attglobal.net> wrote:
> [snip]
>
>> The design is tested. Individual gates are not - or so I've been told
>> by Intel engineers - or any other hardware engineers I've worked with.
>> They don't even test individual gates in SSI chips, which have very few
>> gates. For instance, they don't test the individual gates in a 7473
>> flip-flop - they just ensure the chip operates correctly.
>
> Your knowledge is outdated. Your knowledge is also second-hand and
> most likely have misunderstood what you were told. As a practicing
> engineer in the field who has practical experience with ASIC and SOC
> designs I can tell you unequivocally that gates are tested, functional
> blocks are tested and the entire design is tested at every step in the
> process, especially before the silicon is produced. Once in production
> the scan chains are tested against the expected patterns and defects
> are investigated and root causes exposed and corrected.
>
Not really - not when I was consulting with the programmers at Intel.
And I can tell you that every one of the millions of gates on a chip is
NOT tested. In fact, in the finished chip, there aren't even ways to
test the vast majority of the gates. What IS tested is the operation of
the chip.
Yes, the design is tested, and within that design, functional blocks are
tested. But if a half adder works, I don't need to test any of the
individual gates.
> SSI chips are another matter entirely and I never mentioned them and
> now you bring them up as some kind of example. Then you cite 7400
> series chips where JTAG is not even feasible due to pin count and TTL
> technology isn't even used in most large scale projects where JTAG is
> an essential part of the validation process. This shows how your
> knowledge of this topic really out of date and obsolescent. Where
> flip-flops (of any technology) are incorporated in the LSI and HSI of
> an ASIC or SOC I can tell you with absolute certainty they are tested
> at the gate level.
>
I'm also not talking about SOC's - YOU brought those up. I'm talking
about Pentiums, I3's, I5's, I7's - these aren't even designed by
engineers. The engineers feed in design specs and the chips are
designed by computers. The output is a logical "chip" which can be
tested in pieces and as a whole. Each gate *could* be tested - but it's
a huge waste of time. A NAND gate is a NAND gate. It will always work
as a NAND gate, and there's no reason to think it won't.
Of course, not everything can be tested - timing, for instance, can
cause problems. So once the design is verified at this level, a mask is
created and prototypes are made. The prototypes are then tested - but
not every gate is tested.
And even with JTAG, it is not feasible to test any of the millions of
gates on a current microprocessor. There aren't nearly enough pins to
do it. In fact, the ration of gates to pins is lower on a 7400 series
chip than it is on any of the current microprocessors. If you can't do
it on a 7400 series chip, you sure as heck can't do it on an I7.
> You don't need to repeat yourself. You need to shut up about a topic
> you know nothing about. Your ignorance is exposed.
>
You should learn to take your own advice.