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About memory visibility..
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amin...@gmail.com
Aug 4, 2019, 4:40:47 PM8/4/19
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Hello,
About memory visibility..
I have come to an interesting subject about memory visibility..
As you know that in parallel programming you have to take care
not only of memory ordering , but also take care about memory visibility,
read this to notice it:
Store Barrier
A store barrier, “sfence” instruction on x86, forces all store instructions prior to the barrier to happen before the barrier and have the store buffers flushed to cache for the CPU on which it is issued. This will make the program state "visible" to other CPUs so they can act on it if necessary.
I think that this is also the case in ARM CPUs and other CPUs..
So as you are noticing that i think that this memory visibility problem is
rendering parallel programming more "difficult" and more "dangerous".
What do you think about it ?
Thank you,
Amine Moulay Ramdane.
About memory visibility..
I have come to an interesting subject about memory visibility..
As you know that in parallel programming you have to take care
not only of memory ordering , but also take care about memory visibility,
read this to notice it:
Store Barrier
A store barrier, “sfence” instruction on x86, forces all store instructions prior to the barrier to happen before the barrier and have the store buffers flushed to cache for the CPU on which it is issued. This will make the program state "visible" to other CPUs so they can act on it if necessary.
I think that this is also the case in ARM CPUs and other CPUs..
So as you are noticing that i think that this memory visibility problem is
rendering parallel programming more "difficult" and more "dangerous".
What do you think about it ?
Thank you,
Amine Moulay Ramdane.
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