INVLPG Instruction

[Henk Nep]

Hi All,

The Intel SW development manual Vol3 states:

"The INVLPG instruction is provided to invalidate a specific
page-table entry in the TLB.
Normally, this instruction invalidates only an individual TLB entry;
however, in some cases, it
may invalidate more than the selected entry and may even
invalidate all of the TLBs."

Does anybody know under what circumstances the INVLPG instruction
clears the whole TLB?

Thanks.

[Robert Wessel]

I'm not aware of any Intel CPU on which it actually does invalidate
the entire TLB, although that doesn't mean there isn't one.

But you're looking at the architectural specification. In hardware it
may be (very) inconvenient to guarantee the absolute minimum number of
TLB entry purges, depending on how exactly the TLB gets indexed. So
they're just saying it may be more than the minimum*, and they've
specified the largest possible maximum.

Section 4.10 of volume #3A goes into this in some detail, especially
the requirements for when you have to do specific invalidations.


*For example, they list as specific examples that INVLPG may delete
TLB entries for the given page for different PCIDs, or that on
multi-threaded processors, TLB entries for one thread may be
invalidated by a different thread.

[CN]

This behavior is CPU model dependent, and it doesn't necessarily mean there
actually is a CPU model that clears the whole TLB. In the architecture document,
it is intentionally left unspecified to make sure people don't rely on a
particular CPU model behavior and write code compatible with any x86 CPU, and
also to leave the CPU manufacturer some space to maneuver.

In other words, you'll write better code if you don't know the answer.