The SIRA framework is a graph theoretical approch four guaranteing the
absence of spilling before instruction scheduling. The methods bounds
the register requirement of a data dependence graph before instruction
scheduling under resource constraints. Our register pressure reduction
strategy is sensitive for both software pipelining (innermost loops) and
acyclic scheduling (basic blocks and super-blocks). We consider
processor architectures with multiple register type and we model delayed
access times to registers. Our register pressure reduction method is
distributed as a C independent library (SIRAlib).
Research report, experimental data and software (LGPL) are available in
http://hal.archives-ouvertes.fr/inria-00436348/fr