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Description: Computer architecture.
 

Call for Papers: World Congress on Engineering and Computer Science WCECS 2013 
  Call for Papers: World Congress on Engineering and Computer Science WCECS 2013 CFP: World Congress on Engineering and Computer Science WCECS 2013 Draft Paper Submission Deadline: 2 July, 2013 Camera-Ready Papers Due & Registration Deadline: 30 July, 2013 WCECS 2013: San Francisco, USA, 23-25 October, 2013... more »
By iaeng_imecs_wce_wcecs_e  - May 20 - 1 new of 1 message    

Fractal heat transfer... 
  Here is the article: [link] IMVHO, this is pretty interesting...
By Chris M. Thomasson  - May 16 - 2 new of 2 messages    

Mill info for those who want details 
  I've been talking informally here for a few months about our Mill general-purpose CPU architecture. In an effort to formalize things a bit, we have set up an info mailing list that you can subscribe to at [link], which will send you on to the list manager.... more »
By Ivan Godard  - May 15 - 1 new of 1 message    

Immediate Position:::Business Analyst With BI EXP::::At Houston, TX 
  Immediate Position:::Business Analyst With BI EXP::::At Houston, TX Hi, This is Girish, - Recruitment and Resources from SancroSoft USA Inc. We have an urgent requirement as follows: Please respond with resumes in MS-Word Format with the following details toGir...@sancrosoftusa.com... more »
By susheel kumar  - May 15 - 2 new of 2 messages    

Find your Lost and Stolen Computer or Laptop 
  Dear Friends, Have you lost your computer or you want to keep trace your computer in future, here is an idea.... I found this link on the internet and would like to share with you... Hope this will be useful for you [link] cheers,... more »
By lakshmi4fri...@gmail.com  - May 15 - 1 new of 1 message    

Computer on a chip... 
  Theoretically, I imagine that it is possible to have a complete computer occupying a single die, of course an MCU is basically this, but taking it to a bigger scale, let's say take a modern X86 processor, and on the die give it RAM and all the peripherals needed to eliminate other IC's on a motherboard. It seems to me that advantages are obvious (reduced latency, more compact motherboard, ect) but what are the problems with realizing this? Complexity? Reliability?... more »
By unixrun...@gmail.com  - May 15 - 23 new of 23 messages    

Possible overheat vunerability in AMD X2 3800+ CPUs 
  Hello, While playing Compay of Heroes Tales of Valor I noticed the computer shutdown a few times. I am now starting to believe that 100% cpu utilization + 100% gpu utilization could have caused a strange/rare case over CPU overheat. (It could also simply be a cause of too many amperes being drawn).... more »
By Skybuck Flying  - May 14 - 4 new of 4 messages    

ssl proxy server 
  ssl proxy server [link]
By 23alagmy  - May 14 - 1 new of 1 message    

Why L1 data cache has a 64-B cache line size, but the linefill buffer is only 32B? 
  I got this question in ARM Tech Reference Manual. quote: "The L1 data memory system has the following features: Data side cache line length of 64-bytes. ...... Two 32-byte linefill buffers and one 64-byte eviction buffer. ......" How line fill operation is conducted? Let's discuss about this interesting issue.... more »
By qili.s...@gmail.com  - May 14 - 2 new of 2 messages    

Practicality of microarchitecture-optimized register allocation? 
  How practical would it be for a compiler to coordinate register allocation with microarchitecture? (Some coordination would be based on ABIs.) E.g., "Implicit Hints: Embedding Hint Bits in Programs without ISA Changes" (Hans Vandierendonck and Koen De Bosschere, 2010) proposed using register names for hints and "Knapsack: A... more »
By Paul A. Clayton  - May 9 - 15 new of 15 messages    

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