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Message from discussion x86 Sequential Consistency
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Joe Seigh  
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 More options Nov 19 2006, 10:50 am
Newsgroups: comp.arch, comp.programming.threads
From: Joe Seigh <jseigh...@xemaps.com>
Date: Sun, 19 Nov 2006 10:50:11 -0500
Local: Sun, Nov 19 2006 10:50 am
Subject: Re: x86 Sequential Consistency
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Elcaro Nosille wrote:
>   Steve Watt schrieb:

>>> What an idiotic advice.

>> Care to elaborate a bit on your opinion of that advice?

> When do you have the opportunity to chose a CPU in s sw-project? Almost never!
> And for learning-purposes? The manual should be sufficient.
> And there's no need for this exact memory-model because there are constraints
> under which synchronization works perfectly on x86s: either through monitors
> or critical sections which use LOCKed operations. Even if this behaviour isn't
> defined excacly: Intel couldn't chage this because most x86-OSes rely on the
> current behaviour. So there's no need to worry about the missing definition
> of the x86 memory-model.

We're talking about knowing what the memory model is so the synchronization
primatives can be implemented correctly.  Right now it's mostly guessing and
erring on the safe side.

Note that discussions like this never occur about the other architectures
like Z arch, powerpc, sparc, etc...

What's worse is the system manufacturers who build Intel based SMP systems
with more processors than Intel supports.  There is no telling what they
may have as a memory model.

> Alexander Terehov is a geek which sees problems that don't exist.

Could be worse.  He could be a non geek who doesn't see problems that
do exist.

--
Joe Seigh

When you get lemons, you make lemonade.
When you get hardware, you make software.


 
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