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Message from discussion x86 Sequential Consistency
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Anton Ertl  
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 More options Nov 20 2006, 5:15 am
Newsgroups: comp.arch, comp.programming.threads
From: an...@mips.complang.tuwien.ac.at (Anton Ertl)
Date: Mon, 20 Nov 2006 10:15:59 GMT
Local: Mon, Nov 20 2006 5:15 am
Subject: Re: x86 Sequential Consistency
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already5cho...@yahoo.com writes:
>2. Implied read dependency barrier

You mean, that, if there is a data (flow) dependence chain between two
loads, the second load will not see an earlier memory state than the
first load?

Does the IA-32 and AMD64 architecture guarantee that?  I know that
IA-64 does and Alpha does not.  Load-address prediction (present in
the Pentium 4 IIRC) can subvert it.

- anton
--
M. Anton Ertl                    Some things have to be seen to be believed
an...@mips.complang.tuwien.ac.at Most things have to be believed to be seen
http://www.complang.tuwien.ac.at/anton/home.html


 
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