David Kanter wrote:1) Get rid of strongly coherent cache. It just generates a lot of cache
> I had a short and semi-unsatisfying discussion of multiprocessing ISAs
> I only got a few responses, so I thought I would try here.
> Suppose you were to build an ISA from scratch, with the primary
traffic that is unnessary. The program mechanisms to indicate when
cache has to be updated are mostly there. Programs have to execute
proper synchronization to get valid data anyway. A program calculation
that is incorrect with data that is 10 msec stale will still be incorrect
even if the data is only 10 pico sec stale.
2) Standardize the interlocked instructions a little better. It is a pain
candidates here: doubleword compare and swap (not DCAS), load locked/store
3) Restartable intervals. These would be instruction intervals that if interrupted
You must Sign in before you can post messages.
To post a message you must first join this group.
Please update your nickname on the subscription settings page before posting.
You do not have the permission required to post.