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Message from discussion Multiprocessor ISA
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Joe Seigh  
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 More options Aug 12 2003, 6:07 am
Newsgroups: comp.arch
From: Joe Seigh <jseigh...@xemaps.com>
Date: Tue, 12 Aug 2003 10:07:45 GMT
Local: Tues, Aug 12 2003 6:07 am
Subject: Re: Multiprocessor ISA
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David Kanter wrote:

> I had a short and semi-unsatisfying discussion of multiprocessing ISAs
> at Real World Tech over the weekend.

> I only got a few responses, so I thought I would try here.

> Suppose you were to build an ISA from scratch, with the primary
> purpose being superior multiprocessor performance on commercial
> workloads.  How would this ISA differ from current high performance
> designs?

1) Get rid of strongly coherent cache.  It just generates a lot of cache
   traffic that is unnessary.  The program mechanisms to indicate when
   cache has to be updated are mostly there.  Programs have to execute
   proper synchronization to get valid data anyway.  A program calculation
   that is incorrect with data that is 10 msec stale will still be incorrect
   even if the data is only 10 pico sec stale.

2) Standardize the interlocked instructions a little better.  It is a pain
   to see these instructions pop in and out of architectures.  Try writing
   anything portable these days.

   candidates here:  doubleword compare and swap (not DCAS), load locked/store
   conditional combined with monitor/mwait.

3) Restartable intervals.  These would be instruction intervals that if interrupted
   would be restarted at beginning of the interval.  This would let you do things
   like implement RCU in user space and get the huge scalability benefits that have
   heretofore been limited to non-preemptive kernels.  Restartable intervals
   can be done in the OS but it would be nice to have hw support.  Kernel developers
   get touchy about adding anything to the main dispatch path.

Joe Seigh


 
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