Account Options

  1. Sign in
The old Google Groups will be going away soon, but your browser is incompatible with the new version.
Google Groups Home
« Groups Home
comp.arch
+ new post
About this group
Subscribe to this group
This is a Usenet group - learn more
Message from discussion Why no double wide compare and swap on Sparc?
The group you are posting to is a Usenet group. Messages posted to this group will make your email address visible to anyone on the Internet.
Your reply message has not been sent.
Your post was successful
 
From:
To:
Cc:
Followup To:
Add Cc | Add Followup-to | Edit Subject
Subject:
Validation:
For verification purposes please type the characters you see in the picture below or the numbers you hear by clicking the accessibility icon. Listen and type the numbers you hear
 
Joe Seigh  
View profile  
 More options Jun 13 2006, 6:24 pm
Newsgroups: comp.arch
From: Joe Seigh <jseigh...@xemaps.com>
Date: Tue, 13 Jun 2006 18:24:19 -0400
Local: Tues, Jun 13 2006 6:24 pm
Subject: Re: Why no double wide compare and swap on Sparc?
Print | View thread | Show original | Report this message | Find messages by this author
Chris Thomasson wrote:
> "Joe Seigh" <jseigh...@xemaps.com> wrote
>>What's with the Sparc architects?

> IMHO, I believe the major reason 32-bit architectures support DWCAS was to
> be "64-bit ready"; DWCAS gets converted to normal CAS on 64-bit systems. So,
> if your 32-bit applications used DWCAS, then they can be run 64-bit arch
> without changes... Of course there is a caveat...

> A 32-bit application cannot use DWCAS to manipulate a pointer along with
> another contiguous variable...

> struct dosent_work_on_64_bit_s {
>   void *a;
>   whatever b;
> };

> IMO, the hardware architects' did NOT have lock-free algorithms in mind when
> they decided to put DWCAS in their 32-bit instruction sets. The fact that
> 128-bit CAS is not reliably supported seems to support my opinion...

IBM S370 had double wide compare and swap long before 64 bit support
became an issue.

>>There's a bit of a disconnect here I think.

> Perhaps they are designing the lock-free algorithms for a upcoming processor
> design. Maybe one that has hardware transactional memory... That could be
> the reason they designed KCSS:

They've done a bit on STM (software transactional memory).  If they did
come out with hardware based transactional memory it would be after the
fact of 64 bit sparc and wouldn't be generally available.  So it would
have to be hidden behind some system or library api with alternate
implementations on non TM platforms.  That would limit its applicability.
For example, you couldn't have atomically thread-safe refcounted smart
pointers.  Well, not without RCU and/or SMR.  If they go with STM to
compliment hw TM, it's only going to work at a lower contention level
if the STM algorihtm is only obstruction-free.

It's a big problem.  You can design efficient synchronization mechanisms
that are portable if you ignore Sparc.  If you want portability to
Sparc you have to sacrifice performance or functionality.

If Sun has a 64 bit JVM implementation, I wonder what they do for
the AtomicMarkedReference and AtomicStampedReference implementations
for non Sparc platforms.  Cripple them so they perform as poorly as
the Sparc implementations?

--
Joe Seigh

When you get lemons, you make lemonade.
When you get hardware, you make software.


 
You must Sign in before you can post messages.
To post a message you must first join this group.
Please update your nickname on the subscription settings page before posting.
You do not have the permission required to post.
Create a group - Google Groups - Google Home - Terms of Service - Privacy Policy
©2013 Google