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Message from discussion Virtual address Memory Protection Unit
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Terje Mathisen  
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 More options Jun 22 2012, 3:22 am
Newsgroups: comp.arch
From: Terje Mathisen <"terje.mathisen at tmsw.no">
Date: Fri, 22 Jun 2012 09:22:35 +0200
Local: Fri, Jun 22 2012 3:22 am
Subject: Re: Virtual address Memory Protection Unit
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MitchAlsup wrote:
> We found that as you scale back the computation power (i.e.
> complexity) ofthe core, you can dramatically scale back to size of
> the TLB. So you might need a 64-entry FA TLB backed up by a 512-entry
> 4-way set TLB for a great big OoO core; you can get away with a
> 32-entry FA TLB fro a core of 1/2 to compute power of its GBOoO
> bretheren.

> Other smaller earlier cores point to a serious disadvantage if/when
> the TLB gets smaller than 24-entries (in any configuration).

Is it even possible to have good performance with a TLB which is too
small to cover the cache hierarchy?

I.e. I remember fondly (NOT!) the Pentium model that had 512 KB L2 cache
but only 64 entries for 4 KB pages, i.e. maximum 256 KB of coverage.

We got very distinct performance knees when the working set passed the
L1 size, the TLB size and the L2 size.

Can you reload TLB entries fast enough (from cache?) that this problem
is ameliorated?

Terje

--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"


 
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