Message from discussion
Itanium finally passes Alpha at HP
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NNTP-Posting-Date: Fri, 27 Aug 2004 12:13:47 -0500
From: "Bill Todd" <billt...@metrocast.net>
Newsgroups: comp.arch,comp.sys.ibm.pc.hardware.chips,comp.sys.intel
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Subject: Re: Itanium finally passes Alpha at HP
Date: Fri, 27 Aug 2004 13:15:04 -0400
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"Alex Johnson" <compu...@jhu.edu> wrote in message
news:cgnb35$673$1@news01.intel.com...
> Bill Todd wrote:
>
> > In 'Beyond Superdome", he first waxes poetic about current Superdome
> > capabilities, such as their internal interconnect fabric. Let's see:
this
> > is the server architecture (at least somewhat reminiscent of the old and
> > rather mediocre GS320 server architecture) that using 64 top-of-the-line
> > Itanics barely manages to stay ahead of the new POWER5 box that requires
> > only 16 processors (on a grand total of 8 chips, since they're
dual-core) in
> > TPC-C, right?
>
> I believe you have misinterpretted the "16 processor" POWER5.
You believe incorrectly.
IBM
> actually refers to chips.
What IBM may or may not 'refer' to (and they're not always very consistent
in this) is not what matters in this case. What matters is how TPC-C counts
processors - and TPC-C counts cores as processors.
"16 processor" as reported is 16 POWER5
> chips, comprised of 32 cores, allowing 64 threads of execution.
Incorrect. It is 16 cores, on 8 chips, allowing 32 threads of execution.
So the
> 64-thread Madison vs the 64-thread POWER5 having similar performance is
> just a sign that things are about equal.
Absolute rubbish. The POWER5 system uses 1/4 as many cores, on 1/8 as many
chips, to achieve 80% of the result. Equating dual-thread SMT to twice as
many cores is the kind of nonsense even someone like Terry probably would
not try to pull off: at *most*, it likely improves the TPC-C throughput of
each core by about 30%, which still leaves each 'raw' (non-SMT) POWER5 core
pumping *well* over twice the TPC-C throughput of each Itanic core (hardly
surprising, since even the 32-core non-SMT POWER4+ system marginally beat
out the 64-processor Superdome in TPC-C).
I'm stunned by how good POWER5
> is. But I know that next year Montecito will go from 1 thread per
> package to 4 threads per package. Itanium will be down to a 16P system
> to compete with IBM's 16P system.
If you consider that having less than half the TPC-C performance of the
POWER5 system with an equal number of cores qualifies as 'competing with'
it, perhaps.
>
> > Then he crows, "HP delivers dual core before Intel" as some kind of
> > significant achievement. Well, maybe. Of course, Sun is delivering
> > dual-core SPARC processors today, and IBM started delivering dual-core
> > POWER4s nearly three years ago. So what beating Intel to the punch
mostly
> > proves is just how far behind the curve Itanic really is, I'd suggest.
>
> And Itanium being behind the curve is a joint decision between intel and
> HP, pushed by HP. If not for staffing levels on Itanium a few years
> back and HP pushing to be the first to do the interesting dual-core
> project, there would have been a dual-core Itanium 2 on the market last
> year.
More bullshit.
Adding staffing to Itanic wouldn't have speeded up the applicable process
technology significantly, so any dual-core Itanic released last year would
still have been in 130 nm. IIRC the current Madison core occupies about 43%
of the space on a 376 mm^2 chip: doubling it would have left no room for
the gargantuan caches that Itanic requires to achieve competitive
performance, not to mention creating a 200W chip to have to cool.
>
> > Doubling
> > current system performance by about a year from now actually sounds
pretty
> > impressive, until you recognize that Superdome's TPC-C performance today
> > with 64 processors falls slightly behind today's
previous-design-generation
> > POWER4+ systems that use only half that number of processors and only
> > slightly manages to beat today's POWER5 boxes that use only 1/4th as
many
> > processors.
>
> As explained above, if you compare per thread, these machines are
> equivalent in size (64P Madison, 32P * 2 cores POWER4+, 16P * 2 cores *
> 2 threads POWER5).
As explained above, that explanation is even more chock-full of shit than
Terry's tend to be.
>
> > When Montecito comes along late next year
> > it will indeed close much of this gap with POWER5 (Terry's second
> > TPC-C-specific performance graph suggests it should slightly exceed 2
> > million tpmC), but POWER5 (a full process generation behind Montecito
but
> > still heading for about 3 million tpmC late *this* year) will no longer
be
> > IBM's top-of-the-line product by then, since POWER5+ (in the same
process
> > generation as Montecito) should then be shipping and upping the ante
> > significantly.
>
> I have not seen these graphs. Could you tell me what configuration
> those X million tpmC results are for? 4P, 16P, 64P, 64 *thread*. How
> are the estimates being made. I don't have a lot of TPC numbers, but I
> know a 4-socket Madison today is 121K and a 4-socket POWER5 (yes, that's
> 16 threads) is 371K and Montecito is supposed to also be around 370K in
> 4-socket. It will be a tight race. If you could explain the
> configurations, that would help me. If you could quote published
> 4-socket numbers for POWER4 and POWER4+, that would help me (I'm trying
> to make a table).
Why don't you try getting a clue what you're talking about first? Learning
something about what SMT is and is not would be a good start. Then try
getting some *quantitative* idea about how much the different SMT
implementations you're so casually throwing together add to the performance
of the core they're associated with.
>
> > And Fujitsu has regular enhancements to SPARC64
> > coming along to keep pace with Itanic (though not POWER), regardless of
what
> > one may think of Sun's future efforts for that architecture.
>
> > SPARC is dead, eh? Or 'no longer relevant', as a later slide says.
> > Someone better tell Fujitsu so it will stop stomping all over the
> > latest Itanics in commercial benchmarks like jbb2000: that's really
> > not suitable behavior for a 'dead' processor. And by all means make
> > sure those HP customers who are defecting to Sun know this: what on
> > earth do you suppose they're thinking?!
>
> Fujitsu is far ahead of Sun in performance, but they are far behind even
> the laggard (intel) when it comes to features.
Except that they seem to be trouncing Intel in jbb2000, and seem likely to
do very well in other commercial benchmarks given Fujitsu's experience in
large-system design. Funny about that.
They say dual-core at
> end of '05, dual-core with 2 threads each sometime in '07. Compare that
> to Montecito which is mid-'05 with dual-core and 2 threads per core.
> Two years ahead.
Or zero years ahead, depending upon how useful Montecito's relatively crude
two-way SMT turns out to be. But even if SPARC64 falls slightly behind
Itanic in performance (a fact decidedly not yet in evidence) it probably
won't hurt Sun: it will still be far more relatively competitive in
performance than any Sun SPARC has been in recent memory, so should if
anything improve Sun's position.
- bill
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