Account Options

  1. Sign in
The old Google Groups will be going away soon, but your browser is incompatible with the new version.
Google Groups Home
« Groups Home
Message from discussion The Emperor's new clothes
The group you are posting to is a Usenet group. Messages posted to this group will make your email address visible to anyone on the Internet.
Your reply message has not been sent.
Your post was successful
 
From:
To:
Cc:
Followup To:
Add Cc | Add Followup-to | Edit Subject
Subject:
Validation:
For verification purposes please type the characters you see in the picture below or the numbers you hear by clicking the accessibility icon. Listen and type the numbers you hear
 
Chris Thomasson  
View profile  
 More options Nov 22 2005, 2:18 am
Newsgroups: comp.arch
From: "Chris Thomasson" <_no_spam_cristom@no_spam_comcast._net>
Date: Tue, 22 Nov 2005 01:18:27 -0600
Local: Tues, Nov 22 2005 2:18 am
Subject: Re: The Emperor's new clothes
"Joe Seigh" <jseigh...@xemaps.com> wrote in message

news:iKudnfC1qrPxZRzenZ2dnUVZ_tGdnZ2d@comcast.com...

> So these processor manufacturers all have these
> nice new multi-core cpu's but apart from market
> hyperbole (these cpu's will save the environment, etc...)
> I don't see them actually doing anything to exploit their
> potential.  By "them", I mean them not us.  We of course
> know to do.  But what's going on to get all the applications
> to start exploiting this?

Well, Intel's current research seems to be moving toward transactional
memory:

http://www.cambridge.intel-research.net/~rennals/faststm.html

In the near future they may be pushing developers to convert their
applications critical sections into transactions. I believe that they are
going to start to advertise transactional memory as a "general solution"
that can directly address the new multi-core processors that are coming out.
If the do take that path, I am not sure how well its going to work out for
them. They will probably need to put a transactional memory implementation
in the hardware itself. Something like this:

http://ogun.stanford.edu/~kunle/publications/tcc_isca2004.pdf

I am not too sure how well this would scale... It seems as though it could
possibly suffer from livelock-like situations under certain circumstances.
For instance, simple false-sharing may cause some transactions to abort. I
think it would be similar to the live-lock that can occur when there is
false-sharing on a LL/SC based lock-free LIFO anchor and/or nodes;
reservation granularity you know...

> The magic parallelization fairy?

Well, the fact that double-width compare-and-swap did not get "reliably"
ported to 64-bit architectures make be think that may be relying on a
magical fairy to come down and show application developers the light...
Luckily there are some algorithms out there (e.g., VZOOM and RCU-SMR) that
can help applications boost performance and efficiently scale-up to the new
multi-core designs right now. However, in order for this stuff to really
take off I believe that its going to take somebody to "bite-the-bullet" and
incorporate one of these solutions into their application architecture. Then
let the performance and scalability improvement(s) speak for themselves...

:)

As of now I am only using VZOOM for in-house projects. Maybe I should do
something commercial with it... Ahhhh, it would probably be a waste of
time... Perhaps I should use it to implement a speedy STM framework, since
transactions seem to be the way things are going to go anyway...

;)


 
You must Sign in before you can post messages.
To post a message you must first join this group.
Please update your nickname on the subscription settings page before posting.
You do not have the permission required to post.