Multiple openings for Digital, Design, USB verification and RTL design engineers Experience: 5-10 years Locations California USA. Apply @ http://embeddedcareers.com/index.php

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For All Jobs:-: Product Domain Expertise: Semiconductor. Skill
Category: ASIC Design. Please apply only if physically present in US.
H1 B, TN Visa, can apply.
DGITAL VERIFICATION ENGINEER
- Minimum 7 years experience in Ascii & system verification, processor
verification, or Ed methodology development.
- Strong knowledge of object oriented hardware verification Languages
such as System Verily or VERA, as well as industry standard hardware
design languages like Verily, VHDL, C & Lerp, and System C.

DESIGN VERIFICATION ENGINEER
1) Block Verification -> System Verilog-OVM skillset. 4 Positions
2) Multi Chip Verification -> Specman- 6 Positions Specman
3) Modem Verification –> Modem IP Verification- Specman- 2 Positions

USB VERIFICATION ENGINEER
• Knowledge of the USB3 protocol and signaling (level 1, level 2)
• Knowledge of the Synopsys USB3 macro is preferred
• Knowledge of C/C++, System Verilog

FPGA EMULATION ENGINEER
* 7 years experience working with emulation platforms
* Expert in FPGA synthesis, place, and route
* Familiar with Verilog RTL design and simulation
* Familiar Xilinx FPGA
* Familiar with schematic capture and circuit board design

VERIFICATION ENGINEER OVM/UVM
Proficiency in advanced Verification techniques, at both a block and
system level, to work with the design engineering team to support
excellence in design principles and practice.
Knowledge and experience performing timing analysis/debug and
implementing design improvements.

LEAD RTL DESIGN ENGINEER
lead role for the RTL Design Engineer.
- block level spec, write RTL. Blocks will reside on AHB/AXI bus so
- familiarity with these bus structures is desired.
- ARM M3/R4/R5 experience nice to have Verilog Write test benches

LOGIC VERIFICTION ENGINEER

Candidates should also have experience with RTL simulators, VCS
preferred, experience specifying and developing test bench components,
specifying, developing, and debugging functional tests, and experience
specifying, implementing and analyzing functional coverage.

PHYSICAL DESIGN ENGINEER
SOC Encounter P&R, PrimeTime, Apache, Caliber
Block builds that range in size from 100K to 1500K placed instances
with flat hierarchy including embedded IP. Note this may also include
padframe blocks.
Individual engineer ownership to include 1-6 blocks depending on
complexity (gate count, # clock domains, congestion, timing closure,
etc….)