Alpha and Super-pipelining
Chris Perleberg
After reading the material available about the Alpha, I noticed that it was
mentioned a few times that the first implementation of the Alpha, the 21064,
is *super-pipelined* as well as superscalar. For example, in "infosheet.txt"
that is available on gatekeeper.dec.com the following is stated:
> Digital's 21064 Microprocessor
> ....
> The 21064 is a super-scalar, super-pipelined implementation of the
> Alpha architecture. Super-pipelined means that an instruction is issued
> to the functional units at every clock tick and the results are
> pipelined. Being super-scalar, the architecture allows the instruction
> unit to issue two instructions per clock tick, resulting in
> significantly higher throughput and performance.
After reading the Data Sheet of the 21064, I find nothing that seems to
indicate the 21064 is super-pipelined, at least in terms of the common
definition of super-pipelined. Is DEC redefining the word "super-pipeline"?
Anybody out there that can explain?
Chris Perleberg
pch...@dcc.uchile.cl
Alexander Essbaum
i always thought super-piplining referred to piplining funtions that would
normally be given a single pipeline stage. ie. if a processor has 4 stages
with delays like:
ifetch 10ns
decode/operand fetch 10ns
execute 20ns
writeback 10ns
you can cut the critical path delay by 10ns if you break the execute into
2 stages:
ifetch 10ns
decode/operand fetch 10ns
execute1 10ns
execute2 10ns
writeback 10ns
the second example is super-piplined.
axel
John Sullivan
>to
>indicate the 21064 is super-pipelined, at least in terms of the common
>definition of super-pipelined. Is DEC redefining the word
>"super-pipeline"?
>Anybody out there that can explain?
Although it's not obvious, this term really applies more to the cache
structure of a CPU pipeline than anything else. (If you don't believe me,
flame away.) Here's the definition that I suggest:
Super-pipelined:
The primary caches in the CPU pipeline are partitioned across two or
more pipeline stages. Because cache access time is often a cycle-time
determining path, the designers have decided to split the time across
more than one cycle. The tradeoff is a faster instruction issue rate
due to a shorter cycle time) versus longer load-execute and
conditional-branch interlocks (leading to a higher CPI.)
The term "super-pipelined" has been widely used (and abused) since the
late 80's. Super-pipelined machines have existed for about 20 years.
--
John Sullivan, Engineer/Computer Development. Email: jj...@cd.amdahl.com
Amdahl Corporation, Sunnyvale CA. Phone: (408)746-4688
Tim Olson
|After reading the material available about the Alpha, I noticed that it was
|mentioned a few times that the first implementation of the Alpha, the 21064,
|is *super-pipelined* as well as superscalar.
|
|After reading the Data Sheet of the 21064, I find nothing that seems to
|indicate the 21064 is super-pipelined, at least in terms of the common
|definition of super-pipelined. Is DEC redefining the word "super-pipeline"?
|Anybody out there that can explain?
I believe some "simple" ALU instructions, such as shift, issue at a
single-cycle rate, but have a 2-cycle latency.
--
-- Tim Olson
Apple Computer Inc. / Somerset
(t...@apple.com)