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Why L1 data cache has a 64-B cache line size, but the linefill buffer is only 32B?
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qili...@gmail.com
May 14, 2013, 5:37:52 AM5/14/13
to
I got this question in ARM Tech Reference Manual.
quote:
"The L1 data memory system has the following features:
Data side cache line length of 64-bytes.
......
Two 32-byte linefill buffers and one 64-byte eviction buffer.
......"
How line fill operation is conducted?
Let's discuss about this interesting issue.
quote:
"The L1 data memory system has the following features:
Data side cache line length of 64-bytes.
......
Two 32-byte linefill buffers and one 64-byte eviction buffer.
......"
How line fill operation is conducted?
Let's discuss about this interesting issue.
Michael S
May 14, 2013, 7:53:38 AM5/14/13
to
More interesting question is why linefill buffers are needed at all.
If you answer this, then understanding of the size will likely come
automatically.
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