Guesstimates please

[Ivan Godard]

Yet another attempt to mine your collective expertise:

In a modern high-end production chip, what percentage of total power and
area are consumed by the actual arithmetic operations, i.e just the
carry tree etc in the ALUs or or other functional units, not the
logistics of getting the instruction to the FU or the data to and from it.

My wild-ass guess is 4%.

I have in mind to use a quote from Omar Bradley in a talk: "Amateurs
study strategy, professionals study logistics" and want a number to back
it up.

[Paul A. Clayton]

Page 15 of Fayé A. Briggs' presentation "Architectural
Directions for Exascale Computing" (2012) shows two pie
charts for *core* power use--"Non Compute-heavy Application"
and "Compute-heavy Application". The former has 6% in
"Integer Execution"; the latter has 75% in "FP Execution"
and 2% in "Integer Execution".

This presumably includes register file power use, so it is
not ALU power; but it might be helpful information anyway.

The next page shows 40% (of compute-heavy) power use comes
from the "uncore" (bring FP down to 45%).

Google indicates the presentation is here:
http://www.intel.com/cd/corporate/education/apac/eng/aaf12/speakers/presentation/516194.htm

[MitchAlsup]

On Friday, May 3, 2013 4:04:53 PM UTC-5, Ivan Godard wrote:
> what percentage of total power and area are consumed by the actual
> arithmetic operations,

In a high end design (3 GHz) something close to 50% of all power is in
the clock and flip flops. The other metric is 33% clock and flop, 33%
leakage, 33% doing things.

This leaves 50% in DRAM pins, L3, L2, L1D, AGU, LSBuffer, ALU, Stations,
Registers, Decode, IFetch, L1I, BPredictor.

I would bet a modern machine uses 2X-3X the power in the Stations, LSBuffer,
Bpredict as it uses in AGU and ALU combinied (simple area weighting).
So, 50%/16 consumers = 3% each for the first case and 2% each for the later
case.

Mitch