Configurable microarchitecture for behavior study?

[Paul A. Clayton]

I wonder if it would be helpful for a larger
processor to support some diversity of configuration
of caches and predictors to examine how programs
would behave with alternative designs.

Using a commodity microprocessor would seem likely
to provide data faster than using an FPGA or a
software simulation.

Cache block and cache way locking would provide some
ability to configure cache characteristics, but
there might be some other tweaks that would not
hinder normal operation yet could facilitate
studying the tradeoffs. (In some microarchitectures
it might be practical to change access delays.)

Disabling of all or part of a branch predictor
component might be useful. I could even imagine
being able to change ROB and issue queue sizes
(perhaps this could be accomplished by supporting
a dummy thread and infinite delay memory addresses
where the dummy thread runs before the simulation
begins??).

Such behavior study might be academically useful
and *might* have some application where the final
target is a more resource-constrained implementation
of the same ISA.

It might well be that existing simulation techniques
are more than adequate and/or that such
configurability would interfere with performance or
energy efficiency (such would almost certainly add
design complexity which could have been otherwise
been spent for more useful/marketable features).

[Paul Colin Gloster]

Well, F.P.G.A.s are configurable, and processor cores available for
F.P.G.A.s can have cache sizes and policies tweaked. After prototyping
with an F.P.G.A., you can try an A.S.I.C., losing configurability.

[Tacit]

On 22 дек, 00:57, "Paul A. Clayton" <paaronclay...@gmail.com> wrote:
> It might well be that existing simulation techniques

> are more than adequate.

Exactly. Moreover, they are fully confugurable and controllable, so
you can simulate and measure anything. But that takes either lot of
time or lot of servers :)

[Paul A. Clayton]

FPGAs have two notable problems with respect to academic
research. 1) There is a lack of advanced hardware designs
available to use in such studies. (Software simulators
have become relatively featureful and widely/freely
available.) 2) FPGAs are not as broadly available as
commodity processors (i.e., "everyone" can be expected to
have access to a personal computer but relatively few will
have access to an FPGA).

Software simulation is very slow but widely available,
FPGA-based simulation has substantial barriers to entry
and is a bit slower (and the tools for generating FPGA
logic for more abstract simulation are probably very
far from mature and readily available).

The proposed mildly configurable hardware would allow
_limited_ simulation at high speed (and so might have
a useful place alongside other techniques). Such
configurability might be useful for increasing yield
(providing more bins), saving energy (a shallow OoO
window might be more energy efficient, e.g.),
supporting specialized operation (e.g., some embedded
systems desire way-locking), or other uses; so the
design effort would not need to be paid for only by
the benefit to research.

I would guess that this idea is, however, even less
useful than tilting at windmills.