Trivial embedded Architecture idea

[Paul A. Clayton]

Might it be useful in a new Architecture with relatively few address
registers to multipurpose the stack pointer by using the more
significant N bits as a 'segment' with the least significant bit of
the segment clear for stack-pointer-based references. The same
segment could then be used for the global/thread-local-storage pointer
with the least significant bit of the segment set and the less
significant (non-segment) bits cleared, using positive offset
addressing.

Such would obviously put an upper bound on the stack size, but the
upper portion of the stack segment could be used for other data
(assuming stack underflow is not a concern)--with virtual addressing
this would probably not be an issue.

Since this is a relatively obvious mechanism, it has probably already
been considered. (Of course, even in the embedded area, new
Architectures are not common.)

Paul A. Clayton
just a technophile