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Description: Field Programmable Gate Array based computing systems.
 

value of the weak pull up resistor on IOBs of Virtex5 
  Hi, Virtex5 datasheet state that there is a optional configurable weak pull-up/pull-down resistor on each IOB. What is the value of that resistor? I looked at the user guide and configuration guide but could not find it.
By Goli  - 8:39am - 2 new of 2 messages    

Is Virtex 4 supported by Jbits ? 
  Hi ! Is Virtex 4 supported by Jbits ?
By swissiyous...@gmail.com  - 7:59am - 1 new of 1 message    

How to input an analog signal to FPGA board for processing? 
  Hello, I am a beginer and have a basic question. My project implemented on FPGA board (which is Spartan3E-1600 Microblaze Development Kit) includes ADC and is supposed to do some digital signal processing of an analog RF signal from 'outside world'. How I can input an analog signal to my FPGA?
By Vagant  - 2:53am - 4 new of 4 messages    

has anyone made PLB_DDR work with 1Gb DRAM chips? 
  I have a design that consists in part, of the DDR interface from the ML403 board, but with two of these 1Gb DDR parts: [link] instead of these 256Mb parts that were on the original ML403: [link]... more »
By Jeff Cunningham  - 12:01am - 1 new of 1 message    

RLC package parasitics 
  In the IBIS model i can find the package parasitics R_pkg, L_pkg and C_pkg ... but what does these values represent? is it the total parasitics of the entire pins of the package? is it for single pins of the package?
By kislo  - May 11 - 2 new of 2 messages    

how to set trigger in ChipScopePro for this 
  Hi all, I have an application where my data refreshes every 10 seconds...It takes so long as I am doing some sort of an averaging over a few million samples and then taking the statistics once in those few million samples.My system clock is of 40 MHz and it's fed from outside through a SMA connector in Virtex2P board. Hence to get... more »
By Pratap  - May 10 - 4 new of 4 messages    

Xilinx ML507 evaluation board (V5FXT70)? 
  A past google-search revealed Xilinx employees saying this board will be equipped with a Virtex5/FXT70. From what I remember, the FXT70 requires a full-seat of ISE Foundation 10.x (or the equivalent evaluation-edition), and won't compile in Webpack 10.x. Is that correct? Looks like I may have to stick with the much more... more »
By TSIuser  - May 10 - 1 new of 1 message    

getting samples from an RF board onto the system 
  hi, I have got an RF board (antenna+ADC+Some signal processing boxes on a board). The output is a 2bit data and a clock (16MHz). I need to store this 2 bit data for 1 second onto my system in some text or binary format for using it in my simulations. What is the best (in very less time) method to do this?... more »
By vits  - May 10 - 2 new of 2 messages    

USB full speed final project proposal 
  I invite you to use free code of a USB full speed project as final work for diploma. The site includes some description of the functionality and main state machines. The code is based on some free cores 8051 and USB function. The PHY is my own code. [link]... more »
By beky4kr@gmail.com  - May 10 - 1 new of 1 message    

Conversion from VERILOG READMEMB to INTEL HEX 
  Conversion from VERILOG READMEMB to INTEL HEX [link]
By beky4kr@gmail.com  - May 10 - 1 new of 1 message    

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