Description:
Field Programmable Gate Array based computing systems.
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Ask about finding maximum and second's maximum number in array is given.
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I am starting to study VHDL. Now, I have to do an exercise with the following content:
I have to define an array of 10 elements ( 8 bit range) ([3,4,2,8,9,0,1,5,7,6] for example). And 10 elements were imported to within 10 clock cycles. The question is find the maximum number and second maximum number in this array after 10 clock cycle.... more »
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Chasing Bugs in the Fog
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I have a bug in a test fixture that is FPGA based. I had thought it was in the software which controls it, but after many hours of chasing it around I've concluded it must be in the FPGA code.
I didn't think it was in the VHDL because it had been simulated well and the nature of the bug is an occasional dropped character on the receive... more »
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HBA tomorrow (Friday) 14th June
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Hi Friday people,
I won't be in on Friday - but Darren P. has kindly agreed to open up
and operate Request Line.
See you on the 21st,
Alan
-- Alan Fitch
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DDR2 Concurrent Auto Precharge
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I have come across a VHDL Free Model Foundry mt47h16m16.vhd which gives
me some errors.
Has anyone else used this model? If so has anyone had issues with twr
timing errors? Am I right in assuming that this model doesn't feature
Concurrent Auto Precharge?
Is DDR2 like SDR SDRAMs where some devices can cope with concurrent... more »
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LOOPGEN-Fast hardware looping VHDL IPs
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The LOOPGEN IP collection provides fast hardware architectures for
implementing nested loop structures. The collection comprises of
three
different architectures (variants), namely:
- HWLU, a mixed-level structural/RTL architecture,
- IXGENB, a behavioral-level and
- IXGENR, a high-performance, pure RTL description of a more... more »
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New soft processor core paper publisher?
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I have a general purpose soft processor core that I developed in verilog. The processor is unusual in that it uses four indexed LIFO stacks with explicit stack pointer controls in the opcode. It is 32 bit, 2 operand, fully pipelined, 8 threads, and produces an aggregate 200 MIPs in bargain basement Altera Cyclone 3 and 4 speed grade 8 parts while consuming ~1800 LEs. The design is relatively simple (as these things go) yet powerful enough to do real work.... more »
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problem with the GTX wrapper in questa
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Hi,
Tools used by me : questa - 10.0c , xilinx - 13.2, ubuntu - 11.04.
I am trying to simulate GTX wrapper (generated from xilinx coregen) in
questasim. Steps followed by me :
1.Compliled the all xilinx library using "compxlibgui" in questasim.
2.Then copy the modelsim.in into the working directory of project.... more »
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A Question about FPGA IO Standard
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hi,
I have a custom designed board with spartan 2 (XC2S150) with some input
data and clk line connected to a peripheral device, the clk level is 3.3V
and FPGA IO standard(not defined in .ucf file so is the default) is LVTTL
and VCCIO is 3.3 and VREF of FPGA is not connected to any voltage.
my problem is, sometimes reading data from peripheral is erroneous and... more »
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Mentor Graphics Precision RTL + LatticeECP3 Versa
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Could I use the Precision RTL with the LatticeECP3 Versa development
kit?
LatticeSemi does provide a one year evaluation license (old version of
the Diamond Design Suite) for this board.
Any experience using this PCI-e based development board with non-
Lattice software?
Thanks
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