Description:
Field Programmable Gate Array based computing systems.
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Read output from external chip using microblaze
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Hi all
I got stuck with my design. I'm planning to use microblaze in ML505 board
to read my full custom chip output and display to hyperterminal.
I've found one tutorial about read DIP switch using microblaze, but here I
want the output of my external chip to be read by microblaze.
I'm confused of the device_ID that I should use in my programming so that... more »
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Logic Glitches in Spartan-3?
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I've got a 24-input AND gate that I'd like to avoid having add another
register delay to before I toss it across a clock boundary.
all_done <= and_reduce(done);
If I just do it, AND it all together without a flop on the output, does
anyone know whether I'll get transition glitches (an output of 1 when... more »
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Announcement: Sigasi integrates with Aldec compiler
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Dear hardware designers,
In its latest release, Sigasi Pro 2.4 integrates with the Aldec
Riviera-PRO simulator to accelerate the design feedback cycle. Check
out this three minute video on how to find and fix errors in seconds:
[link]
You can download Sigasi 2.4 and get a free evaluation license from our... more »
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ITU656 to Mpeg4 with Fpga?
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An ADV7181BBSTZ - PAL/NTSC Video Decoder coverts an analogue video
camera signal to ITU656 and YCrCb 4:2:2 [[link]
Serial_digital_interface Serial digital stream]. Convert this to JPEG
over Ethernet with a FpGa as implemented by the SoC Milkymist
project.
Ques: Where would one option an IP for this?... more »
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Xilinx ISE Multiple Drivers Error
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Hi folks,
I seem to have convinced ISE to output incorrect multiple-driver error
messages. I've reduced the example to the following:
-- test.vhd
library ieee;
use ieee.std_logic_1164.all;
entity Test is
port(
Clock : in std_ulogic;
Foo : out std_ulogic;
Bar : out std_ulogic);
end entity Test;... more »
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banks and its association with options
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oops,
After discussing about the banks, it is certainly appropriate to take into account the monitoring of the options wisely;
could you explain how to extend banks data management?
Yours, sincerely
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Spartan-6 66mhz pci
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I'm trying to make a simple PCI interface in a XC6SLX45. In the end
I'll probably go with the premade Xilinx core but I wanted to get
familiar with the details first. It seems that the chip simply cannot
meet the timing for this under any circumstances. I've use the UCF
pinouts created for the xilinx core hoping this includes some magic.... more »
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Synthesis Problem
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I have this code written in verilog for a counter but my program xilinx ise
14.1 finds 2 errors:
ERROR:Xst:899 - "numarator9.v" line 45: The logic for <counter_out> does
not match a known FF or Latch template. The description style you are using
to describe a register or latch is not supported in the current software... more »
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FDE vs latch?
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What's the big deal about a latch? Is it less efficient in floorspace than an FDE? Or is it just some amount of combinatorial concerns? For example:
tsc_start <= tsc when sof_in_n = '0' and rising_edge(clk);
versus
tsc_start <= tsc when sof_in_n = '0';
What concerns are there with crossing clock domains with either? For... more »
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