Description:
Field Programmable Gate Array based computing systems.
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XILINX Artix-7 DDR2-RAM-Controller
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Hello,
I'm trying to implement a DDR2-RAM-Controller for the ARTIX-7 FPGA and I have some "problems"
during generation of the simulation models from the MIG-tool. Only the top-level of the DDR2-memory-controller
is generated in VHDL, the instantiated moduls are generated in Verilog.
This is a problem, because I don't have a mixed-language simulator.... more »
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Linting tool setup
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Greetings all,
Further to previous thread(s), has anyone here experience in setting up a
linting tool such as Spyglass or LEDA? How long did it take?
My thoughts are that a suite of test-case files is needed to test for
detection of each code breach, and that preparing that would take a week or... more »
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Xilinx SDK 14.5 debug
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I have a Microblaze design in SDK that I am trying to debug. I have an IP
block with some registers that I can read and write. I have opened a new
memory monitor window so I can see the registers updating. The trouble is
that if I do a write to a register then the monitor does not update. I have... more »
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Reconfigurable Computing - FPGA, Embedded, VLSI, ASIC based designs
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Dear Fellow Students and Researchers,
I am sharing one useful announcement for those who are interested in writing and publishing research papers in the field of Reconfigurable Computing - FPGA, Embedded, VLSI, ASIC based designs.
Please have a look to the following call for paper on Reconfigurable Computing.... more »
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The UK Device Developers' Conference - Last call
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Hi, [link]
Just a final call, to say that we have a few places still available at each
of the Conference locations. Although some workshops are now sold out,
there are a few places still available on others. The Bristol event is next Tuesday (14th), Cambridge (16th) and Manchester... more »
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Any experience of Equivalence Checking tools?
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Greetings all,
Has anyone hereabouts any experience with the use of Equivalence Checking
tools in an FPGA context, for instance OneSpin EC-360 or Mentor FormalPro?
Thanks in anticipation,
Robert
------------------------------ --------- Posted through [link]... more »
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DEP function development on a low budget
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Is it at all practical for home-builders on a very limited budget to develop DSP type functions, such as filters and the like, on FPGAs? Reading around, I get the impression that experimenters that do it have access to high powered tools, through their work or some other way. Tools such as Matlab... more »
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FPGA Development Board with hard PowerPC
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I am working on a channel emulator which is based on a FPGA development
board and a custom based RF board connected to the FPGA board via daughter
card connection (240 pins). I was using WARP 2 (Hard PowerPC Processor in
the FPGA) till now, but am looking for a new FPGA board as WARP 2 is
discontinued because Xilinx has stopped the manufacture of SystemAce. Below... more »
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