Description:
Field Programmable Gate Array based computing systems.
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Life after XDL
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If you know and love XDL or XDLRC, and if you believe that the research
community's access to these tools provides a benefit to Xilinx, this is
your opportunity to speak up. The xdl tool will no longer be available
as of ISE 14, and unofficial word is that Xilinx does not intend to
provide equivalent capability. We don't believe they're deliberately... more »
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Problem with post-route simulation
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The whole ISE project (VHDL) can be found here:
[link]
Besides ISE project, it also contains two print-screen GIFs,
behavioral.gif and post-route.gif.
behavioral.gif shows
@40ns : start = 1, data = AAAA
at next rising CLK edge CS goes LOW
then, SDI serially transmits data (101010...)... more »
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Free GUI top level integration tool for Verilog and VHDL
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VTC has been developed for very long time. It has been used in many
projects and proven to be useful. It should have been available for
you long time ago. But I have to spend many years to study laws alone
to face to the lawyers from leading EDA, because the counsel fee is
too expensive for me. Not long ago, finally my patent was judged to be... more »
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Xilinx Artix-7 availability
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did anybody hear something about the availability about the Xilinx Artix-7 series?
Especially I am interested in the XC7A8 or XC7A15 in the FTG256 Package.
regards
Arne
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A smallish starter Kit for led control
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I would like to see what kind PWM LED control I could do with FPGA and
of course just play with the kit to see what else I can do with it. A
FPGA (kit)with plenty of pins and low price is good.
I am not willing to re invent all the the wheels there is and
programming some PC interface, so the kit or FPGA should have some... more »
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Virtex6HXT PCIe doesn't come up to Gen2 on Sandy Bridge systems
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I have an 8X PCIe core in a Virtex6HXT (version 2.5, the latest in 13.4). It's configured for Gen2 but it's coming up Gen1. lspci -vvv reports that both the core and the board are Gen2 capable. I've looked at the PIPE interface in Chipscope and the board is advertising Gen1 speeds only. Xilinx support said that there is an issue with Sandy Bridge chipsets and... more »
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Difference between Xilinx isim and modelsim
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Is it allowed to pass a member of a std_logic_vector to the rising_edge
function?
When doing this, isim doen's detect all changes, while modelsim does.
The code below toggles bits of a 3-bit vector. Bit 1 of the vector is
checked for rising and falling edges by directly passing vec(1) to
reising_edge(). Bit 1 is also assigned to a scalar signal which is also... more »
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