Discussions - comp.arch.fpga

	Solutions Manuals, Instructor Manuals, Test Banks collection 2012
	Hello, We would like to inform you that we have updated our list with the following new titles. You can contact us directly at Student.p24(at)Hotmail(dot)com . If the title you are looking for is not listed, do not hesitate to contact us, we will try to help. ========== 2011 Federal Taxation, 5th Edition 2011, Pratt.Kulsrud, Instructor... more » By stu.p24 - 7:42am - 1 new of 1 message

	Dangling all pins, DIA0 through DIA31
	I'm creating a dual-port ROM, both sides are the same: 7-bit address, 32-bit data. Very simple ISE 13.3 project can be downloaded from here: [link] Both Implementing and Generating the bit file gives warning like this one: PhysDesignRules:812 - Dangling pin <DIA0>... more » By aleksa - Feb 10 - 7 new of 7 messages

	Call for Papers: The 2012 International Conference of Parallel and Distributed Computing (ICPDC 2012)
	Call for Papers: The 2012 International Conference of Parallel and Distributed Computing (ICPDC 2012) CFP: The 2012 International Conference of Parallel and Distributed Computing (ICPDC 2012) ...Draft Paper Submission Deadline: 6 March, 2012 Camera-Ready papers & Registration Deadline: 31 March, 2012... more » By iaeng_imecs_wce_wcecs_e - Feb 10 - 1 new of 1 message

	ONLY FOR YOUTH
	BOLLYWOOD ACTRESS APSARA AWARDS 2012 [link] AISHWARYA RAI LATEST HOT PICS [link] KATRINA KAIF HOT MAGAZINES PHOTOS [link]... more » By sowji - Feb 8 - 1 new of 1 message

Life after XDL

If you know and love XDL or XDLRC, and if you believe that the research community's access to these tools provides a benefit to Xilinx, this is your opportunity to speak up. The xdl tool will no longer be available as of ISE 14, and unofficial word is that Xilinx does not intend to provide equivalent capability. We don't believe they're deliberately... more »

By Neil Steiner - Feb 7 - 1 new of 1 message

	Problem with post-route simulation
	The whole ISE project (VHDL) can be found here: [link] Besides ISE project, it also contains two print-screen GIFs, behavioral.gif and post-route.gif. behavioral.gif shows @40ns : start = 1, data = AAAA at next rising CLK edge CS goes LOW then, SDI serially transmits data (101010...)... more » By aleksa - Feb 6 - 4 new of 4 messages

	Call for Papers & Sessions: The 2012 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'12), USA, July 16-19, 2012
	CALL FOR PAPERS PDPTA'12 The 2012 International Conference on Parallel and Distributed Processing Techniques and Applications Date and Location: July 16-19, 2012, Las Vegas, USA [link] You are invited to submit a full paper for consideration. All accepted... more » By A. M. G. Solo - Feb 6 - 1 new of 1 message

	'x' state on one bit of the input bus of an adder cause the output bus be all 'x' during simulation
	I have an adder: module adder( input [1:0] add1, input [1:0] add2, output [2:0] addout ); assign addout = add1 + add2; endmodule The input is: add1 = 2'bx0; add2 = 2'b00; The RTL simulation result is: addout = 3'bxxx; The Timing simulation result is: addout = 3'b0x0; and this is what I expected.... more » By Haiwen - Feb 6 - 4 new of 4 messages

Free GUI top level integration tool for Verilog and VHDL

VTC has been developed for very long time. It has been used in many projects and proven to be useful. It should have been available for you long time ago. But I have to spend many years to study laws alone to face to the lawyers from leading EDA, because the counsel fee is too expensive for me. Not long ago, finally my patent was judged to be... more »

By vtxsupp...@hotmail.com - Feb 5 - 1 new of 1 message

	Xilinx Artix-7 availability
	did anybody hear something about the availability about the Xilinx Artix-7 series? Especially I am interested in the XC7A8 or XC7A15 in the FTG256 Package. regards Arne By Arne Pagel - Feb 4 - 5 new of 5 messages

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