Description:
Field Programmable Gate Array based computing systems.
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Sinewave generation
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Assuming a 16.758 MHz sample rate, what's the best way to generate a 2.333333 MHz sine wave in an FPGA? I could use a look-up table, but since the least common multiple of both frequencies is very high, and I have only limited memory, this is surely not optimal. The sampled sinewave for a down-conversion application.... more »
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Ralph Lauren polo
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Ralph Lauren polo - luxury-fashion.org Ralph Lauren polo shirts is very famous and this brand has set up new trademarks in the history of clothing's. They are very comfortable to style on and show off. Being very flaunty in appearance and great in style, they give a cool and casual look to the person. Wholesale Ralph... more »
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free software/open source projects and FPGA?
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I'm trying to look into the status of free software/open source efforts relating to FPGA (because rms asked me to). After searching in this group, wikipedia, etc., the one I've been able to find is slipway/abits from Adam Megacz (Adam, are you still here?), but from checking out the sources it seems development stalled a while... more »
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Microblaze performance in V6
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I was wondering if someone has tried this and has numbers? Any comparison with PPC440 in V5 would also be very much appreciated? Thanks, /Mikhail
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Xcell Journal Issue 69: FPGAs in the Networked Battlefield
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Hi folks, we just finished publishing the fall edition of Xcell Journal, which has a cover story focus on the expanding role of FPGAs in the Global Information Grid. The issue also has a lot of great methodology and how-to content. We're now making it available in a one- click download as well as in the Ceros (flash) format. I hope you... more »
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OK Xilinx users, it's time I was let in on the joke...
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I've had it up to the eyeballs with Xilinx tools now. I'm seriously ready to go postal in the lobby of Xilinx HQ. I don't expect perfection but this really is beyond a joke. Can someone please put me out of my misery, and finally admit that you have _all_ been having me on for the past few years now! :O ...that it has... more »
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Does anyone ever use placement?
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Do any of you advanced users ever use the floorplanning tools to do placement? I'm not talking about placing clock buffers or other individual items, I'm talking about ASIC style floorplanning for units and sub-units. I've asked AE's about that and the response is always to let the tool do placement. So I'm asking experts: Do you ever floorplan, and if so why?... more »
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BRAM reconfiguration problem using OPB_HWICAP on Virtex 4
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Hello! I am trying to use partial reconfiguration to change the contents of BRAM belonging to USER IP. I am able to read the BRAM FRAME, but not able to write (details about frame contents below). XPS 10.1 (lin64) OPB_HWICAP 1.10a, FPGA Virtex 4(xc4vlx25) Here is the example: Buffer after frame read:... more »
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CPLD + MCU SoC from Cypress, free samples too!
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both free samples and 49$ starterkit available, my should be airborn right now somewhere between Paris and my place. The CPLD is small, 190MC, but it still much more then the 16MC availabel in ADI's ADuCs or ST's uPSD devices. PSoC 5, Cortex based devices will probably only be available next year Antti... more »
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