Account Options

  1. Sign in
The old Google Groups will be going away soon, but your browser is incompatible with the new version.
Google Groups Home
« Groups Home
comp . arch . fpga
This is a Usenet group - learn more
Find or start a Google Group about fpga.
Group info
Language: English
Group categories:
Computers
More group info »
Discussions
View:  Topic list, Topic summary Topics 1 - 10 of 33465  Older »
Description: Field Programmable Gate Array based computing systems.
 

Call for Papers: World Congress on Engineering and Computer Science WCECS 2013 
  Call for Papers: World Congress on Engineering and Computer Science WCECS 2013 CFP: World Congress on Engineering and Computer Science WCECS 2013 Draft Paper Submission Deadline: 2 July, 2013 Camera-Ready Papers Due & Registration Deadline: 30 July, 2013 WCECS 2013: San Francisco, USA, 23-25 October, 2013... more »
By iaeng_imecs_wce_wcecs_e  - May 19 - 1 new of 1 message    

XILINX Artix-7 DDR2-RAM-Controller 
  Hello, I'm trying to implement a DDR2-RAM-Controller for the ARTIX-7 FPGA and I have some "problems" during generation of the simulation models from the MIG-tool. Only the top-level of the DDR2-memory-controller is generated in VHDL, the instantiated moduls are generated in Verilog. This is a problem, because I don't have a mixed-language simulator.... more »
By Bodo  - May 18 - 1 new of 1 message    

Linting tool setup 
  Greetings all, Further to previous thread(s), has anyone here experience in setting up a linting tool such as Spyglass or LEDA? How long did it take? My thoughts are that a suite of test-case files is needed to test for detection of each code breach, and that preparing that would take a week or... more »
By RCIngham  - May 15 - 4 new of 4 messages    

Xilinx SDK 14.5 debug 
  I have a Microblaze design in SDK that I am trying to debug. I have an IP block with some registers that I can read and write. I have opened a new memory monitor window so I can see the registers updating. The trouble is that if I do a write to a register then the monitor does not update. I have... more »
By maxascent  - May 11 - 1 new of 1 message    

Reconfigurable Computing - FPGA, Embedded, VLSI, ASIC based designs 
  Dear Fellow Students and Researchers, I am sharing one useful announcement for those who are interested in writing and publishing research papers in the field of Reconfigurable Computing - FPGA, Embedded, VLSI, ASIC based designs. Please have a look to the following call for paper on Reconfigurable Computing.... more »
By cfp.hctlo...@gmail.com  - May 10 - 1 new of 1 message    

The UK Device Developers' Conference - Last call 
  Hi, [link] Just a final call, to say that we have a few places still available at each of the Conference locations. Although some workshops are now sold out, there are a few places still available on others. The Bristol event is next Tuesday (14th), Cambridge (16th) and Manchester... more »
By richard13  - May 9 - 1 new of 1 message    

Any experience of Equivalence Checking tools? 
  Greetings all, Has anyone hereabouts any experience with the use of Equivalence Checking tools in an FPGA context, for instance OneSpin EC-360 or Mentor FormalPro? Thanks in anticipation, Robert ------------------------------ --------- Posted through [link]... more »
By RCIngham  - May 9 - 3 new of 3 messages    

DEP function development on a low budget 
  Is it at all practical for home-builders on a very limited budget to develop DSP type functions, such as filters and the like, on FPGAs? Reading around, I get the impression that experimenters that do it have access to high powered tools, through their work or some other way. Tools such as Matlab... more »
By Bruce Varley  - Apr 26 - 6 new of 6 messages    

FPGA Development Board with hard PowerPC 
  I am working on a channel emulator which is based on a FPGA development board and a custom based RF board connected to the FPGA board via daughter card connection (240 pins). I was using WARP 2 (Hard PowerPC Processor in the FPGA) till now, but am looking for a new FPGA board as WARP 2 is discontinued because Xilinx has stopped the manufacture of SystemAce. Below... more »
By studywireless  - Apr 25 - 3 new of 3 messages    

Low cost and/or small size CPU in an FPGA 
  What is the lowest cost and/or the smallest CPU in an FPGA. Can a CPU with reasonable code space fit into a 44 pin FPGA ? Are there any 44 pin FPGAs ? hamilton
By hamilton  - Apr 24 - 10 new of 10 messages    

1 - 10 of 33465   « Newer | Older »

XML