PowerPC somehow unstable at 300 MHz
Michael Schöberl
I've got a Virtex2P-30 (sg6) and I'm trying to use one
of the PowerPC-cores at 300 MHz (in a system much like
xapp640). The Processor runs at 300 MHz, PLB 100 MHz,
OPB 50 MHz, our clock source is a low-jitter 100 MHz
oscillator.
Sometimes the system behaves wierd and it all looks
like the processor crashes. Running the system at
only 200 MHz (instead of 300) seems to solve all
those problems ...
but is this really the solution?
or is the problem just hidden?
what am I doing wrong?
I think 300 MHz is still within the specs ..
are there any issues at that speed?
is the DCM placement critical at 300 MHz?
The system is built with EDK/ISE 6.3 and our DCM has
DLL_FREQUENCY_MODE = "LOW" and DFS_FREQUENCY_MODE = "HIGH"
and meets all the constraints.
thanks for any hints ...
bye,
Michael
Symon
How about your PCB layout? Or your PDS? Got enough juice and decoupling
caps?
HTH,Syms.
John McCaskill
Hello Michael,
Are you generating the clock with a DCM? I had a problem with a V4FX
and EDK/ISE 8.1 that sounds related to yours.
The timing analyzer will propagate your jitter constraints through a
DCM, but does not account for the jitter introduced by the DCM, which
at 300 MHz is not trivial. I worked around the issue by increasing the
jitter spec on my clock, so that after it had been propagated through
the DCM it accounted for both the jitter of my clock, and the jitter
introduced by the DCM.
Regards,
John McCaskill
Brian Davis
>
> what am I doing wrong?
> I think 300 MHz is still within the specs ..
> are there any issues at that speed?
> is the DCM placement critical at 300 MHz?
>
thoughts on DCM problems:
Assuming you've covered all the basics ( clean power,
same bank SSO OK, proper DCM constraints and attributes,
static timing met, appropriate DCM resets and DCM-in-lock-
with-CLKFX-working status bit monitoring logic, DCM
startup works in simulation, FPGA not overheating )
Q1) What is the DCM topology used to generate all of
those related clocks? ( any DCM cascade, which
DCM outputs in use, etc)
Q2) How are you loading your bitstream onto the FPGA?
( JTAG / PROM / other )
Q3) What are the topside markings on your V2Pro ?
Q4) How many parts/boards exhibit this problem ?
Have you looked at:
- V2Pro errata for your chip version/stepping
- Answer Record 13756
basic DCM care and feeding
- Answer Records 14425,19005
proper DCM startup and reset
- Answer Record 10972
other DCM status bits to monitor
- XAPP685
"Duty Cycle Distortion" correction macro for V2Pro DCM's
+ corner DCM's have problems in some parts
- Answer Record 15130
magic bitgen "Centered_x#y#" option setting for DCM
zeroes phase shift delay tap setting
- Answer Record 20585
certain small integer CLKFX ratios don't work
magic bitgen "PLcentered_x#y#" option
zeroes clkfx setting
- Answer Record 11778
DCM startup issues with JTAG download
post listing other DCM quirks:
http://groups.google.com/group/comp.arch.fpga/msg/6e5b0b6da92b4ad1
Other suggestions:
- Is the DCM locked to a specific location near both the clock
input and BUFG? Often the tools will do a horrible automatic
placement, routing the DCM nets up and down the chip spine
instead of placing such that direct connects can be used.
- If you suspect a high frequency duty cycle problem, in addition
to the bitgen "center" options, also try changing the DCMs'
DESKEW_ADJUST to SOURCE_SYNCHRONOUS
( which disables the DCM feedback delay line )
- Monitor the internal clock by using a DDR output FF, forwarding
the clock ( Answer Record 12406 ) through a terminated LVDS
output buffer appropriately probed by a high BW scope.
Brian
Michael Schöberl
> caps?
The regualtors are PTH05000 (6 Amps) and they deliver the
correct voltage (they are not yet at the limit)
I was pretty confident about the layout but the ripple on
my supply voltages is +- 100mV (on 2.5V and 1.5V) ...
I guess that might be too much for 300 MHz operation?
bye,
Michael
Michael Schöberl
> thoughts on DCM problems:
wow - that is a pretty long list - thanks!
I'm pretty sure we didn't looked at all of that
I'll let you know when I find out ...
A1) the topology is simply a 100MHz LVDS-oscillator feeding
one DCM for 50/100/300
A2) I'm loading with JTAG or cclk - same problem
A3) the markings on my V2P are hidden under a heat sink
(I'll check if there is one board without it)
A4) we did some tests on 4 boards - all of them show
the same problem
bye,
Michael
Michael Schöberl
> my supply voltages is +- 100mV (on 2.5V and 1.5V) ...
> I guess that might be too much for 300 MHz operation?
all the beginner's problems ...
with a differential probe the ripple is just +-20 mV
bye,
Michael
Michael Schöberl
> thoughts on DCM problems:
We checked a lot of docs and learned a lot about
DCMs ... but it turned out that the PPC was and
is working fine!
The problem was with the timing of our the flash chip
and some rounding in the wait routine. This caused
setup/hold to be around the limit of "somehow working"
and sometimes failing at 300 MHz :-/
again - thanks for the good ressource list ...
bye,
Michael