Mapping port for simulation only in VHDL

[arkaitz]

Hi all,

I would like to use a signal in the a testbench that is declared in
one of the subblocks of the top.

This question might obvious, but I cannot find any other way to
use subblock signals from a top of a design ONLY for simulation
purposses.

What I usually do is to add those signals as ports in each entity
beginning from the bottom of the design and continuing the hierarchy
until I arrive to the top. In order not to consider them in the
synthesis I add "synthesis translate off/on" comments.

Here you are an example:

Imagine that I want to instantiate the internal signal of the
subblock1 from the top

entity top is
port(
-- synthesis translate_off
tb_out : out std_logic;
-- synthesis translate_on
...
);
end top;

architecture arch of top is
begin

uut: subblock1
port map(
-- synthesis translate_off
internal => tb_out,
-- synthesis translate_on
...
);
end;

Then I instantiate the top in the same way from the testbench.

I know that in verilog there is another way to refer to a signal that
is declared in subblock, just with something like this:

"top.subblock1.internal"

Any suggestion?

Thanks in advance,

Arkaitz.

[Stefan Frank]

On 05/12/2004 02:44 PM, arkaitz wrote:
> Hi all,
>
> I would like to use a signal in the a testbench that is declared in
> one of the subblocks of the top.
>
> This question might obvious, but I cannot find any other way to
> use subblock signals from a top of a design ONLY for simulation
> purposses.
>
> What I usually do is to add those signals as ports in each entity
> beginning from the bottom of the design and continuing the hierarchy
> until I arrive to the top. In order not to consider them in the
> synthesis I add "synthesis translate off/on" comments.
>

See the following links. They show you simulator dependent and
independent solutions.

<http://www.vhdl.org/vi/comp.lang.vhdl/FAQ1.html#monitor>

<http://tinyurl.com/2gyo2>

<http://tinyurl.com/3h83e>

And please post further VHDL questions to comp.lang.vhdl.

I hope this solves your problem :-)

Tschoe,
Steff

[arkaitz]

Hi Steff,

Thanks a lot for your help. I'm sorry about the posting mistake.
I didn't know that there was a specific forum for VHDL.

Arkaitz.