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Newsgroups: comp.arch.fpga
From: Brad Ree <brad....@programmable-products.com>
Date: 1999/10/07
Subject: Re: External Cloking of Altera MAX 7000S
Not to be picky, but the 7000 family is not an FPGA. This device is
actually an EPLD (Altera terms) or CPLD(Xilinx terms). The reason for this is that this device has a PLD structure, which is the AND/OR array feeding into registers. These EPLDs and FPGAs can not work with a crystal as the clock source. You "Moussa A. Ba" wrote:
> Good day, I am very new to FPGA design so excuse my ignorance. I just > finished simulating my first FPGA design. The simulated is based on a > 4Mhz clock. After burning the circuit on the chip and supplying my > external clock through a 4 Mhz crystal, the clock gets totally messed up > as soon as it is connected to the fpga clock input, am I suffering from > loading problem? Is there any other way to provide a reliable clock to > the system. By the way, the board I am using is the UP1 board > university program. > Thank you in advance You must Sign in before you can post messages.
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