External Cloking of Altera MAX 7000S - comp.arch.fpga

Message from discussion External Cloking of Altera MAX 7000S

davezz9472

More options Oct 21 1999, 3:00 am

Newsgroups: comp.arch.fpga

From: davezz9...@my-deja.com

Date: 1999/10/21

Subject: Re: External Cloking of Altera MAX 7000S

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MAX7000S is 5V part but is also compatible with 3.3V I/O. VCCIO pins
are the I/O voltage pins. VCCINT pins are the internal logic power
pins. If your design use 5V only both of them will be connected to 5V.
If you want interface to 3.3V parts, then you need connect VCCIO to
3.3V supply.

In article <37FE7BBC.BCF86...@eng.umd.edu>,
Moussa Ba <b...@eng.umd.edu> wrote:

> The board I am using is the University Program Altera board that
features a
> MAX7000S as well as a FLEX10K chip. I did notice that on the pinout
of the
> MAX7000S it had a bunch of VCCIO, VCCINT and GND pins. In my pin
description
> file it mentions that these pins have to be connected to 5.0,5.0 and
GND
> respectively. I assumed that these pins were directly driven by the
on-board
> power supply. Is my assumption wrong? I did test out the pins and
they provide
> no Voltage. Do I have to provide that voltage?

> Moussa
> Mike wrote:

> > Moussa Ba wrote in message <37FD1D45.848CC...@eng.umd.edu>...
> > >Thank you for your reply. I forgot to mention in my email that I
did use a
> > TTL
> > >crystal oscillator. And I still get a messed up signal as soon as
I
> > connect the

> > >clock to the clock input of the MAX chip.

> > Is it possible that you connect your clock to a wrong pin? Check
how your
> > pins were routed in your .rpt file. It sounds like you are
connecting your
> > clock to a pin configured as an output.

> > Mikhail Matusov

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