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Message from discussion Simple ADS5273 -> Xilinx Interconnect Model
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Brian Davis  
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 More options Mar 10 2006, 12:17 am
Newsgroups: comp.arch.fpga
From: "Brian Davis" <brimda...@aol.com>
Date: 9 Mar 2006 21:17:13 -0800
Local: Fri, Mar 10 2006 12:17 am
Subject: Re: Simple ADS5273 -> Xilinx Interconnect Model
  I've put together a preliminary slide showing before/after
eye diagram comparisons of the ADS5273 -> V4 interface:

 - IBIS/HyperLynx models  vs.  simple SPICE model
 - no back termination    vs.  6mA back term + attenuation scheme

  Plots are temporarily at the following location until I update the
original file:
  ftp://members.aol.com/fpgastuff/temp_plots.pdf

  Many thanks to Symon for running those HyperLynx sims for me,
and for reminding me that real world current sources are less
reflective away from midstream than ideal ones .

Setup:
 - simple lossless models as originally described in <lvds_current.pdf>
 - PRBS-5 data pattern
 - note varying scales on plots

Comments:

   Again, I'd not trust either method without lab verification;
 see notes below for specific concerns, particularly regarding
 the DC offset seen on the Xilinx IBIS input models.

   In any case, I'd say the plots clearly show the improvement
 in ISI crossing jitter and eye closure over the direct connection.

   The back terminated version also significantly reduces the
 peak-peak reflected junk at the pins of the precision mixed
 signal A/D. (bearing in mind real world Tlines have more loss)

   The two simulation methods match fairly well, but there's a
 smaller eye opening in the SPICE model than in the IBIS plots.

   I think they'd match much better without the huge DC offset
 in the IBIS models, which seems to be causing the driver to
 saturate and/or clamp in the Hyperlynx sims.

   This causes the asymmetrical TX overshoot in the lower left
 IBIS plots, the imbalance from which then causes the squiggle
 in the leading edge of the IBIS Rx crossing waveform.

 IBIS model concerns:

   - Xilinx v4 IBIS model for LVDS inputs generates IBIS parser
     warnings about non-zero clamp currents

   - V4 IBIS model pulls up LVDS driver output common mode
     from the expected 1.2V to around 1.5V

   - DT terminator modeled as simple resistor in IBIS files;
     how much does it vary over allowed input range of diff Rx?

 Spice model concerns:

   - ideal current source model of the driver is perfectly reflective,
     unlike an actual device which can't swing past its headroom

   - 9 db may be too much with real world Tline loss at weak driver
    corner  ( reduce attenuation or remove/change 100 ohm back term )

Brian


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