Newsgroups: comp.arch.fpga
From: "Brian Davis" <brimda...@aol.com>
Date: 9 Mar 2006 21:17:13 -0800
Local: Fri, Mar 10 2006 12:17 am
Subject: Re: Simple ADS5273 -> Xilinx Interconnect Model
I've put together a preliminary slide showing before/after
eye diagram comparisons of the ADS5273 -> V4 interface: - IBIS/HyperLynx models vs. simple SPICE model Plots are temporarily at the following location until I update the Many thanks to Symon for running those HyperLynx sims for me, Setup: Comments: Again, I'd not trust either method without lab verification; In any case, I'd say the plots clearly show the improvement The back terminated version also significantly reduces the The two simulation methods match fairly well, but there's a I think they'd match much better without the huge DC offset This causes the asymmetrical TX overshoot in the lower left IBIS model concerns: - Xilinx v4 IBIS model for LVDS inputs generates IBIS parser - V4 IBIS model pulls up LVDS driver output common mode - DT terminator modeled as simple resistor in IBIS files; Spice model concerns: - ideal current source model of the driver is perfectly reflective, - 9 db may be too much with real world Tline loss at weak driver Brian You must Sign in before you can post messages.
To post a message you must first join this group.
Please update your nickname on the subscription settings page before posting.
You do not have the permission required to post.
| ||||||||||||||