A constant value of 0 in block
YiQi
following warings:
WARNING:Xst:1989 - Unit <memoryctr>: instances <Mcompar__n0319>,
<Mcompar__n0290> of unit <LPM_COMPARE_1> are equivalent, second
instance is removed
WARNING:Xst:1710 - FF/Latch <memData_8_17> (without init value) has a
constant value of 0 in block <memoryctr>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch
<memData_8_16> (without init value) has a constant value of 0 in block
<memoryctr>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch
<memData_5_17> (without init value) has a constant value of 0 in block
<memoryctr>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch
<memData_4_17> (without init value) has a constant value of 0 in block
<memoryctr>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch
<memData_3_17> (without init value) has a constant value of 0 in block
<memoryctr>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch
<memData_2_17> (without init value) has a constant value of 0 in block
<memoryctr>.
WARNING:Xst:1294 - Latch <Mtridata_sramIO1_0> is equivalent to a wire
in block <memoryctr>.
... ....(from <Mtridata_sramIO1_0> to <Mtridata_sramIO1_15>)
WARNING:Xst:1294 - Latch <Mtridata_sramIO1_15> is equivalent to a wire
in block <memoryctr>.
WARNING:Xst:1710 - FF/Latch <X_31> (without init value) has a constant
value of 0 in block <memoryctr>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <X_9>
(without init value) has a constant value of 0 in block <memoryctr>.
... ...(from <X_9> to <X_30>)
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <X_30>
(without init value) has a constant value of 0 in block <memoryctr>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Y_11>
(without init value) has a constant value of 0 in block <memoryctr>.
... ...(from <Y_11> to <Y_31>)
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Y_31>
(without init value) has a constant value of 0 in block <memoryctr>.
mostly are having a constant value of 0 in block <XXX>.
The program is target in a Spartan3 starter board to read and/or write
8 addresses after the incoming address(currentX, currentY) chanages.
Although it isn't follow the coding examples, it setup as a state
machine.
=================
Here is the code:
=================
entity memoryCtr is
Port ( direction : in std_logic_vector(2 downto 0);
currentX : in std_logic_vector(7 downto 0);
currentY : in std_logic_vector(7 downto 0);
reset : in std_logic;
enable : in std_logic;
ready : out std_logic;
action : in std_logic_vector(1 downto 0);
front : out std_logic_vector(15 downto 0);
fright : out std_logic_vector(15 downto 0);
right : out std_logic_vector(15 downto 0);
bright : out std_logic_vector(15 downto 0);
back : out std_logic_vector(15 downto 0);
bleft : out std_logic_vector(15 downto 0);
left : out std_logic_vector(15 downto 0);
fleft : out std_logic_vector(15 downto 0);
clk : in std_logic;
sramIO1 : inout std_logic_vector(15 downto 0);
sramCE1 : out std_logic;
sramUB1 : out std_logic;
sramLB1 : out std_logic;
--sramIO2 : inout std_logic_vector(15 downto 0);
sramAddr : out std_logic_vector(17 downto 0);
--sramCE2 : out std_logic;
--sramUB2 : out std_logic;
--sramLB2 : out std_logic;
sramWE : out std_logic;
sramOE : out std_logic
);
end memoryCtr;
architecture Behavioral of memoryCtr is
constant mapSize: integer := 256; -- 128*128
constant memSize: integer := mapSize/2; -- memSize -> 0 ->
memSize
type memDatas is array (8 downto 0) of std_logic_vector(17 downto 0);
-- the value for memory location
type state_type is (init, setup, read, write, outEnable);
signal state: state_type := init;
begin
memLoop: process(clk)
variable addr :integer;
variable readyEnable: std_logic := '1';
variable X, Y :integer;
variable prevAction : std_logic_vector(1 downto 0) := "00";
variable tempData1, tempData2 : std_logic_vector(15 downto 0) :=
x"0000";
variable FmemData, FRmemData, RmemData, BRmemData,
BmemData, BLmemData, LmemData, FLmemData : std_logic_vector(15
downto 0);
variable memData: memDatas; -- the location for 8
memories
variable dir : integer := 8; -- direction counter
begin
----------------------------------------------------------------------------------------
----------state 1: accept calls and initialize the calls for current
location ----------
----------------------------------------------------------------------------------------
if reset = '1' then
state <= init;
ready <= '0';
dir := 8;
readyEnable := '1';
sramWE <= '0';
sramOE <= '0';
sramAddr <= (others => '1');
sramCE1 <= '1';
sramUB1 <= '1';
sramLB1 <= '1';
sramIO1 <= (others => 'Z');
else
case state is
when init =>
ready <= '0';
if enable = '0' then
readyEnable := '0';
elsif enable = '1' AND dir < 0 then
readyEnable := '0';
elsif enable = '1' AND dir > 0 then
readyEnable := '1';
end if;
dir := 8;
-- calulate and place the current address in the memory bus
if clk = '1' AND readyEnable= '1'
then
if currentX = "1000000" AND currentY = "1000000" then
front <= x"1111";
fleft <= x"1111";
left <= x"1111";
bleft <= x"1111";
back <= x"1111";
bright <= x"1111";
right <= x"1111";
fright <= x"1111";
state <= init;
else
X := CONV_INTEGER(currentX);
Y := CONV_INTEGER(currentY);
addr := CONV_INTEGER(Y)*mapSize+CONV_INTEGER(X);
if action = "01" AND prevAction = "01" then
tempData1 := FmemData;
FmemData := FRmemData;
FRmemData := RmemData;
RmemData := BRmemData;
BRmemData := BLmemData;
BLmemData := LmemData;
LmemData := FLmemData;
FLmemData := tempData1;
dir := -1;
state <= outEnable;
elsif action = "10" AND prevAction = "10" then
tempData1 := FLmemData;
FLmemData := LmemData;
LmemData := BLmemData;
BLmemData := BRmemData;
BRmemData := RmemData;
RmemData := FRmemData;
FRmemData := FmemData;
FmemData := tempData1;
dir := -1;
state <= outEnable;
else
memData(0) := CONV_STD_LOGIC_VECTOR(addr-mapSize, 18);
memData(1) := CONV_STD_LOGIC_VECTOR(addr-mapSize+1, 18);
memData(2) := CONV_STD_LOGIC_VECTOR(addr+1, 18);
memData(3) := CONV_STD_LOGIC_VECTOR(addr+mapSize+1, 18);
memData(4) := CONV_STD_LOGIC_VECTOR(addr+mapSize, 18);
memData(5) := CONV_STD_LOGIC_VECTOR(addr+mapSize-1, 18);
memData(6) := CONV_STD_LOGIC_VECTOR(addr-1, 18);
memData(7) := CONV_STD_LOGIC_VECTOR(addr-mapSize-1, 18);
memData(8) := CONV_STD_LOGIC_VECTOR(addr, 18);
dir := 8;
state <= setup;
end if;
prevAction := action;
end if;
end if;
----------------------------------------------------------------------------------------
----------state 2: setup the buses for read
--------------------------------------------
----------------------------------------------------------------------------------------
when setup => -- for read
ready <= '0';
sramCE1 <= '1';
sramUB1 <= '1';
sramLB1 <= '1';
sramWE <= '0';
sramOE <= '1';
if dir = 8 then
sramAddr <= memData(dir);
elsif CONV_INTEGER(direction)+dir > 7 then
sramAddr <= memData((CONV_INTEGER(direction)+dir-8));
else
sramAddr <= memData((CONV_INTEGER(direction)+dir));
end if;
sramIO1 <= (others => 'Z');
state <= read;
----------------------------------------------------------------------------------------
----------state 3: clear the bus, read the current value,& write if
necessary ----------
----------------------------------------------------------------------------------------
when read => -- reading and break the output before next read or
write
ready <= '0';
sramWE <= '0';
sramOE <= '0';
tempData1 := sramIO1;
sramIO1 <= (others => 'Z');
if tempData1 = "UUUUUUUUUUUUUUUU" OR -- Address have not been
visit,
tempData1 = "0000000000000000" OR -- calculate and place
tempData1 = "XXXXXXXXXXXXXXXX" then -- new data and update it
-- go to write state
state <= write;
elsif action = "11" AND dir = 8
AND X /= memSize AND Y /= memSize then --update the entry
state <= write;
else -- go to output stage
state <= outEnable;
end if;
----------------------------------------------------------------------------------------
----------state 4: write the calcualted value to current entry
-------------------------
----------------------------------------------------------------------------------------
when write => -- updating the value for a entry
ready <= '0';
-- perparing the value
if dir = 8 then -- current location
if tempData1 = "0000000000000000" then -- empty entry
if abs(memSize - X) > abs(memSize - Y) then
tempData1 := CONV_STD_LOGIC_VECTOR(abs(memSize - X), 16)+1;
else
tempData1 := CONV_STD_LOGIC_VECTOR(abs(memSize - Y), 16)+1;
end if;
else -- update entry
tempData1 := tempData1 +1;
end if;
else -- surrounding location
if CONV_INTEGER(direction)+dir > 7 then
X := abs(memSize -
(CONV_INTEGER(memData(CONV_INTEGER(direction)+dir-8)) mod mapSize));
Y := abs(memSize -
(CONV_INTEGER(memData(CONV_INTEGER(direction)+dir-8))/mapSize));
else
X := abs(memSize -
(CONV_INTEGER(memData(CONV_INTEGER(direction)+dir)) mod mapSize));
Y := abs(memSize -
(CONV_INTEGER(memData(CONV_INTEGER(direction)+dir))/mapSize));
end if;
if X > Y then
tempData1 := CONV_STD_LOGIC_VECTOR(X, 16);
else
tempData1 := CONV_STD_LOGIC_VECTOR(Y, 16);
end if;
end if;
-- follow signal did not change since setup
sramCE1 <= '1';
sramUB1 <= '1';
sramLB1 <= '1';
sramWE <= '1';
sramOE <= '0';
sramIO1 <= tempData1;
state <= outEnable;
----------------------------------------------------------------------------------------
----------state 5: check if all done, yes then output all the values
-------------------
---------- else back to setup stage
-------------------
----------------------------------------------------------------------------------------
when outEnable => -- if all done then output state
sramWE <= '0'; -- just a safe to clear the bus again
sramOE <= '0';
sramIO1 <= (others => 'Z');
if dir = 0 then
FmemData := tempData1;
end if;
if dir = 1 then
FRmemData := tempData1;
end if;
if dir = 2 then
RmemData := tempData1;
end if;
if dir = 3 then
BRmemData := tempData1;
end if;
if dir = 4 then
BmemData := tempData1;
end if;
if dir = 5 then
BLmemData := tempData1;
end if;
if dir = 6 then
LmemData := tempData1;
end if;
if dir = 7 then
FLmemData := tempData1;
end if;
dir := dir - 1;
if dir >= 0 then -- back to setup stage
state <= setup;
else -- all done, send the output the cooresponding
port
ready <= '1';
front <= FmemData;
fright <= FRmemData;
right <= RmemData;
bright <= BRmemData;
back <= BmemData;
bleft <= BLmemData;
left <= LmemData;
fleft <= FLmemData;
state <= init;
end if;
when others =>
state <= init;
end case;
end if;
end process;
end Behavioral;
Any help on this would be greatly appreciated.
Thanks very much in advance.
YiQi
YiQi
"WARNING:Xst:1294 - Latch <latch_name> is equivalent to a wire in block
<block_name>."
Solution 1:
This problem is fixed in the latest 5.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 5.1i Service Pack 1.
Above message from Xilinx's web site, But I am using 7.1i already, it
isn't that my errors should be fixed?
Mike Treseler
> The following warning is issued:
> isn't that my errors should be fixed?
Try fitting your code into a template like this
begin
if reset = '1' then
init_regs;
elsif rising_edge(clock) then
update_regs;
end if;
update_ports;
end process sync_template;
-- Mike Treseler
It is not in the stars
to hold our destiny but in ourselves.
-William Shakespeare
YiQi
For such a big program, it is very hard to follow 100% of the template.
My code is already in that structure, except that it doesn't have to
work in rising_edge(clock) for the else part.
One thing I really want to ask is does "equivalent to a wire in block"
warning seriously important on synthesis? Is it saft to ignore that?
What I am more worry is the " a constant value" warning, I think I have
to fix that as it may totally check my code.