placing addiional caps across existing caps to reduce noise
Austin Lesea
To the subject at hand: placing additional caps across existing caps
does not reduce the noise (unless the dominant cause is lack of adequate
capacitance).
The reason why the noise is bad is that the L (as in Ldi/dt) is most
likely the largest, and most dominant factor, in the form of the via and
traces to the bypass capacitor.
Many times people have placed additional caps on top of the the existing
caps and wondered why the noise is not reduced: well, you did not
change the L in the equation, did you. So why did you expect V to change?
You may have moved the resonant frequency (more often not), but often
people make the mistake of assuming that a 0.1uF requires a 0.01uF and a
0.001uF in parallel. You can see that if the series L is dominant, you
haven't even moved the frequency by more than a few percent by the small
amount of additional capacitance.
Unfortunately, once the via and trace L is large, there is no way to
make the noise less, withpout making a whole new pcb (re-layout).
More that once we have had to inform a customer that there is "no hope"
for their pcb because the series L in their layout is dominant, and
there is no way to reduce it.
And, we have then helped them re-layout their pcb and making their
system work just fine (as, if you know what you are doing, this is not a
hard problem to solve).
Mark Alexander's power distribution application note represents the
latest state of our power distribution sysem "knowledge."
As we learn more, we will certainly update the applications note.
Again, my apologies to the group for a new thread, on an old subject.
Austin
fpga...@yahoo.com
Austin Lesea wrote:
> Unfortunately, once the via and trace L is large, there is no way to
> make the noise less, withpout making a whole new pcb (re-layout).
>
> More that once we have had to inform a customer that there is "no hope"
> for their pcb because the series L in their layout is dominant, and
> there is no way to reduce it.
This is certainly true, and been the cause for more than a few
re-layouts.
At the same time, the chip carrier PCB in most BGA packages also has
via's (probably a lot smaller) which add to the series L which are
beyound your control, so you only have half, or less of the series L
variable in your control. This is even more difficult with older BG
series parts where there are also bonding wires in the equation.
The only reason for stacking a mix of caps in checkout, is just to
verify that it's not a bulk capacitance problem.
It would be nice if Xilinx specified both the R and L for these chip
carrier PCB's vias/traces, along with chip carrier interplance
capacitance, and current profiles to better model both power system
performance, and I/O performance. Or at least gave firm numbers on what
the user PCB values can be, before the combine result would be unstable
by design.
rickman
> To the subject at hand: placing additional caps across existing caps
> does not reduce the noise (unless the dominant cause is lack of adequate
> capacitance).
>
> The reason why the noise is bad is that the L (as in Ldi/dt) is most
> likely the largest, and most dominant factor, in the form of the via and
> traces to the bypass capacitor.
>
> Many times people have placed additional caps on top of the the existing
> caps and wondered why the noise is not reduced: well, you did not
> change the L in the equation, did you. So why did you expect V to change?
>
> You may have moved the resonant frequency (more often not), but often
> people make the mistake of assuming that a 0.1uF requires a 0.01uF and a
> 0.001uF in parallel. You can see that if the series L is dominant, you
> haven't even moved the frequency by more than a few percent by the small
> amount of additional capacitance.
What do you think about the idea that if the caps are connected
directly to good low impedance power planes that the location of the
caps are not critical at all. I have been discussing this in
comp.arch.embedded and have not gotten much negative feedback except
some claim that more is always better and that multiple values are not
needed.
A recent SI/EMI class I took says that you can put a relatively small
number of caps pretty much anywhere on the board as long as they are
coupled to the power planes with no traces, just the via. This gives a
very low impedance connection to the planes and the planes give a very
low impedance connection to the chip. It was also shown that to get a
low impedance over a broad bandwidth multiple values are needed to push
the impedance down and the parallel resonance up. High loss capacitors
(X7R/X5R vs. C0G) were also recommended to reduce the signficance of
the parallel resonance.
Does any of this sound correct to you? It was sure convincing in the
class and appears to be a very sure way of getting low noise on the
power planes and thereby on the chip power pins!
fpga...@yahoo.com
rickman wrote:
> What do you think about the idea that if the caps are connected
> directly to good low impedance power planes that the location of the
> caps are not critical at all. I have been discussing this in
> comp.arch.embedded and have not gotten much negative feedback except
> some claim that more is always better and that multiple values are not
> needed.
On proto boards I'm always worried about process controls, and
frequently avoid flying probe testing since it only tests a small
number of the connections anyway. One of the concerns has always been
plating managment, so where I can on proto (and most production boards)
I still place the caps across the pwr/gnd vias when I can, simply to
take the via/plane plating reliability out of the question. Stacking
caps on problem boards, is just a second check, as high frequency caps
are the only thing at the pads normally, so a little bulk stacked on it
just takes the via plating out of the question a bit.
On production boards, the vendors will generall work with you to
optimize plating density across the board, so it's much less of a
problem.
rickman
If you have problems with via plating, don't you have much bigger
problems to worry about than cap placement?
fpga...@yahoo.com
rickman wrote:
> If you have problems with via plating, don't you have much bigger
> problems to worry about than cap placement?
On production boards, it's simply not acceptable.
On proto boards, it's only a problem for high current vias (pwr/gnd),
which is largely avoided if that's where the caps are too, since it
averages out the current spikes and reduces any voltage drop across the
bad plate. Even then, the few places that it was a problem at all,
where the small BGA vias ... everything else is large enough you never
see it.
fpga...@yahoo.com
rickman wrote:
> If you have problems with via plating, don't you have much bigger
> problems to worry about than cap placement?
I suppose you can always break out the micro/milli ohm meter and double
check every power ground via to plane .... but it's just easier to add
bulk caps as a check for problem boards, since the BGA is already
mounted anyway, and no way to reliably ohm it.
Uwe Bonnes
> To the subject at hand: placing additional caps across existing caps
> does not reduce the noise (unless the dominant cause is lack of adequate
> capacitance).
> The reason why the noise is bad is that the L (as in Ldi/dt) is most
...
On that subject:
The webpages for Spartan 5 talk about "Virtex-5 sparse chevron packaging
effectively positions bypass capacitors on-substrate"
I didn't find any further information about these capacitors.
--
Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Antti
Spartan-5 ? is Spartan-4 going to be skipped?
Antti
Uwe Bonnes
Kolja Sulimma
> You may have moved the resonant frequency (more often not), but often
> people make the mistake of assuming that a 0.1uF requires a 0.01uF and a
> 0.001uF in parallel. You can see that if the series L is dominant, you
> haven't even moved the frequency by more than a few percent by the small
> amount of additional capacitance.
Larger caps can contribute a significant portion to the L. In that case
the second capacitor helps because you reduce part of the L by adding a
smaller L in parallel to a portion of the big L.
The inductance for an SMT capacitor is in the range of 50pH to 3000pH.
This is about the same range as vias of various sizes.
Kolja Sulimma
Austin Lesea
Via in pad (basically no trace) is best. Placement is not critical, as
long as you have via in pad, and planes.
But even so, the diameter of the vias, and their lengths can be
critical, and still be the dominant factor.
It is all about the lop that is formed (see the HK sparse chevron
presentations, as I think he said it best).
Do you need a broad low impedance? I would say that it is most unusual
that a pcb has to work over all frequencies. The system is usually
designed with a finite number and range of clocks (33 MHz, 266 MHz, 78
MHz, for example). I would counter that rather than a flat broad low
impedance, you could do better to target just the frequencies you care
about.
High loss/low loss is a red herring: I have never seen a case where the
type of capacitor made any difference at all. I would be interested if
anyone has made a board where high loss/loss loss caps actually made a
measurable difference,
Austin
Austin Lesea
The on-chip capacitors are a compromise. They are intended to improve
the energy storage (reduce supply sag, reduce jitter, etc.) but they are
not intended to be the entire solution, nor should they affect the
overall PDS design. Given that we have room for maybe 16 total
capacitors, and their values (each) is ~0.1uF, they are at best useful,
and at worst, provide little improvements at all.
Since we can not choose these values for a specific operation frequency,
they may be useful for only some frequencies, and not useful at others.
We have worked with customers who wish to completely model everything,
and when we supply the geometric model (suitable for Ansoft, or other
E&M tool), we also supply the capacitors for that package being modeled.
I would say that for the 0.1% of customers who are pushing the part to
its absolute limits in their design, that these capacitors may be
important, and they may be required (as input values) in order to
properly optimize/design the rest of the PDS.
If you desire more information about a particular package, please
contact your FAE, who will be able to contact the factory to get the
values, and on what supplies, the internal capacitors are.
Austin
Austin Lesea
I think you are doing extremely well if your cap inductance is dominant.
I have seen many cases where the vias and traces to the capacitors are
more than 1 nH.
Many do not realize just how bad a small diameter via going through half
a pcb can be.
Austin
fpga...@yahoo.com
Austin Lesea wrote:
> Many do not realize just how bad a small diameter via going through half
> a pcb can be.
Ahmen ....
rickman
> Rick,
>
> Via in pad (basically no trace) is best. Placement is not critical, as
> long as you have via in pad, and planes.
>
> But even so, the diameter of the vias, and their lengths can be
> critical, and still be the dominant factor.
>
> It is all about the lop that is formed (see the HK sparse chevron
> presentations, as I think he said it best).
Where exactly is the loop you are referring to? Some would say it is
back to the chip through the power pins. It appears to me that it only
has to include the power planes. If it is back to the chip, then
placement should be critical.
I understand what you are saying, but I think the Ritchey method is
very simple and effective. The range of change in the inductance of
the various via placements is not so large that it swamps out the
inductance of the cap which I would say dominates. In any event, if
you just use a range of cap values to provide multiple SRFs you end up
with a very broad low impedance power plane. This was shown both in
simulation and in measurements.
> Do you need a broad low impedance? I would say that it is most unusual
> that a pcb has to work over all frequencies. The system is usually
> designed with a finite number and range of clocks (33 MHz, 266 MHz, 78
> MHz, for example). I would counter that rather than a flat broad low
> impedance, you could do better to target just the frequencies you care
> about.
Ritchey also discussed this, since knowing your frequency range is
actually critical to any power decoupling approach. He showed that the
IO noise for a series damped transmission line can be calculated
assuming a current profile of the rise time limiting the slew (max
freq) and the duration controlled by the roundtrip delay (min freq).
This trapezoid has a given spectral profile which is not controlled by
the clock at all. So even if the entire design is run from the same
clock you can expect a lot of power noise to show at a wide range of
frequencies.
> High loss/low loss is a red herring: I have never seen a case where the
> type of capacitor made any difference at all. I would be interested if
> anyone has made a board where high loss/loss loss caps actually made a
> measurable difference,
I can't say a design failed because of low loss caps, but Ritchey had
very clear measurements that showed a strong ESR peak where the caps
resonated with the plane. By using caps with a higher ESR the
resonance was damped out and the impedance "hole" was eliminated.
BTW, one of your people was in the class. He seemed to get a lot from
it too. I have misplaced his card or I would ask you to say hi to him
for me. He seemed like a good guy! :^)
fpga...@yahoo.com
rickman wrote:
> I understand what you are saying, but I think the Ritchey method is
> very simple and effective. The range of change in the inductance of
> the various via placements is not so large that it swamps out the
> inductance of the cap which I would say dominates. In any event, if
> you just use a range of cap values to provide multiple SRFs you end up
> with a very broad low impedance power plane. This was shown both in
> simulation and in measurements.
I got the impression from somewhere, that the bga carriers that are
direct die attach also have their own power and ground planes, so that
an individual chip pwr/gnd couples to those planes, which are then
coupled in parallel to the users PCB power planes. It seems that if
this is true, and Xilinx provided both some serious bulk capacitance
and mixed high speed, that the current profiles thru the parallel vias
to the users pcb should be much calmer, and not have a lot of
harmonics. The planes would probably be a hacked up mesh at best, but
better than 4mil traces.
> I can't say a design failed because of low loss caps, but Ritchey had
> very clear measurements that showed a strong ESR peak where the caps
> resonated with the plane. By using caps with a higher ESR the
> resonance was damped out and the impedance "hole" was eliminated.
Hmmm ... that explains some experimental data, thanks!! And contrary to
this thread, why stacked cap debug configurations sometimes seem to
actually work since the 0.1uf and 1uf "bulk caps" stacked over the
0.01uf would have a different ESR's and help damp this by flattening
the current profile in both the cap's and via's inductive response. The
0.01uf caps high current recharge path would be the two bulk caps
instead of resonating with the pwr/gnd plane, and the 0.1uf would more
slowly reduce the current source to the via inductor, tapering off
rather than more abruptly running out of charge early, thus
smoothing/damping the via inductors resonate current response.
Or did I miss something?
rickman
> I got the impression from somewhere, that the bga carriers that are
> direct die attach also have their own power and ground planes, so that
> an individual chip pwr/gnd couples to those planes, which are then
> coupled in parallel to the users PCB power planes. It seems that if
> this is true, and Xilinx provided both some serious bulk capacitance
> and mixed high speed, that the current profiles thru the parallel vias
> to the users pcb should be much calmer, and not have a lot of
> harmonics. The planes would probably be a hacked up mesh at best, but
> better than 4mil traces.
I guess in theory the planes on the BGA could resonate with the board
power planes and produce a pretty high frequency hole, but that would
largely depend on the inductance of the connection and I expect you
would need to measure that to see how bad it is.
Mostly it is important to design low impedance, broadband power planes
and then I would treat the package as inductance in the path to the
chip causing ground/power bounce. Adding caps or planes to the package
will not mitigate the bounce problem.
> Hmmm ... that explains some experimental data, thanks!! And contrary to
> this thread, why stacked cap debug configurations sometimes seem to
> actually work since the 0.1uf and 1uf "bulk caps" stacked over the
> 0.01uf would have a different ESR's and help damp this by flattening
> the current profile in both the cap's and via's inductive response. The
> 0.01uf caps high current recharge path would be the two bulk caps
> instead of resonating with the pwr/gnd plane, and the 0.1uf would more
> slowly reduce the current source to the via inductor, tapering off
> rather than more abruptly running out of charge early, thus
> smoothing/damping the via inductors resonate current response.
I'm not sure your analysis is accurate, but it is a rare case where
adding caps will hurt. The smallest cap will produce the highest
frequency parallel resonance. Any lower frequency parallel resonance
will be mitigated by the capacitive effect of the smaller cap. It is
hard to analyze this stuff by thinking about it. It is much better to
simulate it or to measure it. If nothing else you can check out the
Ritchey book, "Right The First Time, A Practical Handbook on High Speed
PCB and System Design, Volume 1". He is promising a Volume 2,
"Included in this text will be a thorough treatment of EMI; a
comprehensive description of the PCB fabrication process and PCB
materials; a detailed examination of simulation tools and their use and
a complete discussion of Gigabit and higher signaling protocols."
KJ
> Rick,
>
> Via in pad (basically no trace) is best. Placement is not critical, as
> long as you have via in pad, and planes.
>
think via in pad creates an assembly issue because the pad of the part
is physically blocking the via (by design). Unfortunately I don't
recall the specifics, maybe someone else recalls.
Unless you already understand the issue (that I've conveniently
forgotten) I would suggest that whoever is going to be building your
boards be consulted to understand if there are appropriate tradeoffs
that can be made prior to planning to use 'via in pad' since
manufacturability is also generally a concern that at least must be
taken into consideration and evalutated.
KJ
John_H
Via in pad is a bad thing if you don't have filled vias since they would
otherwise wick the solder away from the component. This "solder thief"
can present a reliability problem beyond initial build because of
trapped gasses even if the connection started out as good.
Filled vias are an extra process that will cost a little money but most
PC vendors can do it. The benefits in lower inductance can be great.
rickman
I would love to see some data to support that statement about the lower
inductance. I don't have Ritchey's book handy, but I seem to recall
that moving the vias from the end of the pads to the side was only a
small delta in total inductance (significantly smaller loop area). I
expect that moving them to the center would be another small delta.
This has to be considered in the context of both the inductance of the
device itself as well as the result on the impedance of the board.
I think you will find that small changes in inductance do not have a
major effect on the utility of the caps. If you use multiple caps with
mutiple values you can get a low impedance over a wide bandwidth with a
minimum number of caps. I have no doubt that using via in pad will
help to raise the resonant frequencies, but I think you will find that
if you do all the other things right it will not make much difference
in the end.
John_H
news:1156861074....@h48g2000cwc.googlegroups.com...
> I would love to see some data to support that statement about the lower
> inductance. I don't have Ritchey's book handy, but I seem to recall
> that moving the vias from the end of the pads to the side was only a
> small delta in total inductance (significantly smaller loop area). I
> expect that moving them to the center would be another small delta.
> This has to be considered in the context of both the inductance of the
> device itself as well as the result on the impedance of the board.
>
> I think you will find that small changes in inductance do not have a
> major effect on the utility of the caps. If you use multiple caps with
> mutiple values you can get a low impedance over a wide bandwidth with a
> minimum number of caps. I have no doubt that using via in pad will
> help to raise the resonant frequencies, but I think you will find that
> if you do all the other things right it will not make much difference
> in the end.
Won't any higher inductance result in the same above-SRF slope? That is,
given the total inductance, it won't matter what the capacitance is once
above an ohm in the impedance vs freq plot.
I've seen good information on Cadence tools based on Sun Microsystems work
that tracks what you've described with Ritchey. A recent Howard Johnson /
Xilinx talk also covered many of these items well without contradiction.
In each case, the lowest inductance achievable was always the goal. The
small deltas may be small in nanoHenrys but are probably a significant
percentage.
Same-side vias are better for a cap than end vias. Vias in pad are better.
Partial vias in pad are best. That's the understanding I got.
A distribution of capacitance can give a superb, flat impedance over a wide
frequency range. Resonance is a problem for low ESR caps too far apart in
frequency such that they cancel each other out with an LC resonance between
the SRFs of the two values. Vias in pads provide better performance.
rickman
> given the total inductance, it won't matter what the capacitance is once
> above an ohm in the impedance vs freq plot.
I'm not sure what you are asking. A different capacitance will not
change the inductive part of the impedance curve and a different
inductance will not change the capacitive part of the curve. What
changes in both cases is the SRF. So you put a few 0.1 uF caps on the
board and a number more of 0.01 uF caps and even more of the 0.001 uF
caps. Each capacitance value needs to have sufficient quantity to
bring the impedance near the SRF low enough to be effective. Then the
capacitive effect of the smaller caps keep the overall impedance low in
spite of the larger caps being inductive. Finally the impedance of the
ground planes keep the impedance low for the highest frequency. Doing
a simulation is always a good thing to be able to see how the parallel
resonances affect the impedance.
> I've seen good information on Cadence tools based on Sun Microsystems work
> that tracks what you've described with Ritchey. A recent Howard Johnson /
> Xilinx talk also covered many of these items well without contradiction.
The contradiction part I don't agree with. Many still argue that the
distance between the IC and the cap is critical and some still say
quantity is more important than variety of SRF. In one of these
threads there was a link to a post by HJ. There were some things in
the HJ post that were not supported by any sort of measurement or even
simulation. I don't recall the details.
> In each case, the lowest inductance achievable was always the goal. The
> small deltas may be small in nanoHenrys but are probably a significant
> percentage.
Not inductance, impedance. I don't care about inductance if I can keep
the impedance low over the frequency range that matters to my design.
The small deltas in inductance only move the SRF, they don't have a
large impact on the impedance after you mix the capacitor values.
> Same-side vias are better for a cap than end vias. Vias in pad are better.
> Partial vias in pad are best. That's the understanding I got.
Yes, but none are really bad and it is a cost (or design/fab effort)
vs. benifit. Same-side vias are pretty much free in all respects. Via
in pad has some design effort if you have not done it before and some
PCB vendors don't like to make them (but that varies). Partial vias (I
assume you mean blind) are very expensive and clearly not worth the
effort unless you are doing some really high freq work. Even then, I
don't think they are needed for making the power delivery work well.
Blind vias might be warranted in the signal path when you get near 10
GHz or so, but this is what I am remembering from the class, not
anything I have seen myself.
Ritchey was pretty impressive because he always uses the simplest
methods and verifies that it will work before he builds the actual
board. I don't beleive he said he has ever used vias in pads even with
near 5 GHz boards.
> A distribution of capacitance can give a superb, flat impedance over a wide
> frequency range. Resonance is a problem for low ESR caps too far apart in
> frequency such that they cancel each other out with an LC resonance between
> the SRFs of the two values. Vias in pads provide better performance.
How much better? If your design is so critical that you need to put
the vias in the cap pads, then likely you need to do a careful
simulation of the power distribution to see exactly what you have
rather than to rely on general guidelines that may or may not allow a
given design to work.
rickman
> given the total inductance, it won't matter what the capacitance is once
> above an ohm in the impedance vs freq plot.
I'm not sure what you are asking. A different capacitance will not
change the inductive part of the impedance curve and a different
inductance will not change the capacitive part of the curve. What
changes in both cases is the SRF. So you put a few 0.1 uF caps on the
board and a number more of 0.01 uF caps and even more of the 0.001 uF
caps. Each capacitance value needs to have sufficient quantity to
bring the impedance near the SRF low enough to be effective. Then the
capacitive effect of the smaller caps keep the overall impedance low in
spite of the larger caps being inductive. Finally the impedance of the
ground planes keep the impedance low for the highest frequency. Doing
a simulation is always a good thing to be able to see how the parallel
resonances affect the impedance.
> I've seen good information on Cadence tools based on Sun Microsystems work
> that tracks what you've described with Ritchey. A recent Howard Johnson /
> Xilinx talk also covered many of these items well without contradiction.
The contradiction part I don't agree with. Many still argue that the
distance between the IC and the cap is critical and some still say
quantity is more important than variety of SRF. In one of these
threads there was a link to a post by HJ. There were some things in
the HJ post that were not supported by any sort of measurement or even
simulation. I don't recall the details.
> In each case, the lowest inductance achievable was always the goal. The
> small deltas may be small in nanoHenrys but are probably a significant
> percentage.
Not inductance, impedance. I don't care about inductance if I can keep
the impedance low over the frequency range that matters to my design.
The small deltas in inductance only move the SRF, they don't have a
large impact on the impedance after you mix the capacitor values.
> Same-side vias are better for a cap than end vias. Vias in pad are better.
> Partial vias in pad are best. That's the understanding I got.
Yes, but none are really bad and it is a cost (or design/fab effort)
vs. benifit. Same-side vias are pretty much free in all respects. Via
in pad has some design effort if you have not done it before and some
PCB vendors don't like to make them (but that varies). Partial vias (I
assume you mean blind) are very expensive and clearly not worth the
effort unless you are doing some really high freq work. Even then, I
don't think they are needed for making the power delivery work well.
Blind vias might be warranted in the signal path when you get near 10
GHz or so, but this is what I am remembering from the class, not
anything I have seen myself.
Ritchey was pretty impressive because he always uses the simplest
methods and verifies that it will work before he builds the actual
board. I don't beleive he said he has ever used vias in pads even with
near 5 GHz boards.
> A distribution of capacitance can give a superb, flat impedance over a wide
> frequency range. Resonance is a problem for low ESR caps too far apart in
> frequency such that they cancel each other out with an LC resonance between
> the SRFs of the two values. Vias in pads provide better performance.
How much better? If your design is so critical that you need to put
John_H
> John_H wrote:
>> "rickman" <gnu...@gmail.com> wrote in message
>> Won't any higher inductance result in the same above-SRF slope? That is,
>> given the total inductance, it won't matter what the capacitance is once
>> above an ohm in the impedance vs freq plot.
>
> I'm not sure what you are asking. A different capacitance will not
> change the inductive part of the impedance curve and a different
> inductance will not change the capacitive part of the curve. What
> changes in both cases is the SRF. So you put a few 0.1 uF caps on the
> board and a number more of 0.01 uF caps and even more of the 0.001 uF
> caps. Each capacitance value needs to have sufficient quantity to
> bring the impedance near the SRF low enough to be effective. Then the
> capacitive effect of the smaller caps keep the overall impedance low in
> spite of the larger caps being inductive. Finally the impedance of the
> ground planes keep the impedance low for the highest frequency. Doing
> a simulation is always a good thing to be able to see how the parallel
> resonances affect the impedance.
The discussion was on inductance with vias. If you have 1nH of series
impedance, at 1 GHz it doesn't matter what your capacitance is, you'll have
a degraded impedance based primarily on th L. If you have 1/4 nH series
inductance, you have a 4x improvement in this high-frequency impedance. L
matters for more than just SRF.
>> I've seen good information on Cadence tools based on Sun Microsystems
>> work
>> that tracks what you've described with Ritchey. A recent Howard Johnson
>> /
>> Xilinx talk also covered many of these items well without contradiction.
>
> The contradiction part I don't agree with. Many still argue that the
> distance between the IC and the cap is critical and some still say
> quantity is more important than variety of SRF. In one of these
> threads there was a link to a post by HJ. There were some things in
> the HJ post that were not supported by any sort of measurement or even
> simulation. I don't recall the details.
Neither the tool nor the talk suggested location is critical. I agree with
you that the distance isn't terribly critical. If you have good planes -
even the swiss cheese under an FPGA - your sub-nH plane inductance to the
more distant cap has an adequate connection. The rule of thumb I understood
was to keep the cap within ~1/10 wavelength of the frequencies of interest.
The placement for a 300 MHz SRF cap is more critical than a 30 MHz SRF bulk
device. I agree with you completely on this. "As close to the pin as
possible" is pretty silly; unless you don't have good planes, then go for
it.
>> In each case, the lowest inductance achievable was always the goal. The
>> small deltas may be small in nanoHenrys but are probably a significant
>> percentage.
>
> Not inductance, impedance. I don't care about inductance if I can keep
> the impedance low over the frequency range that matters to my design.
> The small deltas in inductance only move the SRF, they don't have a
> large impact on the impedance after you mix the capacitor values.
The small deltas in inductance directly affect the impedance above the SRF
when the L is dominant on the impedance. The frequency of interest may be
above the SRF but the cap still makes a darn good bypass, retaiing the low
(though increasing) impedance as the frequency increases above the Series
Resonant Frequency.
>> Same-side vias are better for a cap than end vias. Vias in pad are
>> better.
>> Partial vias in pad are best. That's the understanding I got.
>
> Yes, but none are really bad and it is a cost (or design/fab effort)
> vs. benifit. Same-side vias are pretty much free in all respects. Via
> in pad has some design effort if you have not done it before and some
> PCB vendors don't like to make them (but that varies). Partial vias (I
> assume you mean blind) are very expensive and clearly not worth the
> effort unless you are doing some really high freq work. Even then, I
> don't think they are needed for making the power delivery work well.
> Blind vias might be warranted in the signal path when you get near 10
> GHz or so, but this is what I am remembering from the class, not
> anything I have seen myself.
For the really high frequencies, the form factor of the board plays a huge
part with open-end transmission line effects felt as the power planes end at
the board edge. The higher inductance lowers your SRFs and increases the
impedance above your SRF-tuned "floor" possibly still within your
frequencies of interest. All the improved inductance delivers in the end is
a better impedance for when you can't provide any better SRFs.
> Ritchey was pretty impressive because he always uses the simplest
> methods and verifies that it will work before he builds the actual
> board. I don't beleive he said he has ever used vias in pads even with
> near 5 GHz boards.
I'll probably look into getting his book - it sounds like good, hard science
and engineering. The rare stuff.
>> A distribution of capacitance can give a superb, flat impedance over a
>> wide
>> frequency range. Resonance is a problem for low ESR caps too far apart
>> in
>> frequency such that they cancel each other out with an LC resonance
>> between
>> the SRFs of the two values. Vias in pads provide better performance.
>
> How much better? If your design is so critical that you need to put
> the vias in the cap pads, then likely you need to do a careful
> simulation of the power distribution to see exactly what you have
> rather than to rely on general guidelines that may or may not allow a
> given design to work.
I would recommend good power distribution simulation. The tools haven't
been so useful and available to the engineers now used to doing IBIS and
spice simulations for signal integrity. The tools that are available aren't
cheap, either. Proper modeling of the current sources are also a bit of a
trick that wouldn't come easy to the average designer.
____
I would guess the biggest need for the extreme measures is bridging between
the discrete capacitors and the disctributed capacitance of the board
planes. At 10 Ghz, one might be relying entirely on the distributed
capacitance. It's the ~1GHz range that might be the hardest to deal with.
Simulations can show how much of a "hole" there is between caps and
distributed capacitance. This hole can be addressed with unusual
capacitors, vias in pad, or simply not addressed at all. Even with solid
engineering, there's still a bit of an art.
I appreciate the refresh and reevaluation of my own stance on capacitors.
Last time I came out about the distributed values, there were a large number
of naysayers in this group. The more real-world literature we have out
there - such as Ritchey's book - and the more engineers that realize the
interplay, the better we'll all be able to design. For us in
comp.arch.fpga, much of our success comes from the silicon vendors providing
good power distribution on both the silicon *and* the packaging since our
BGAs start to lose sight of the board impedance above many of the
frequencies we're worrying about. Discretes on our boards are still
affected by our power decoupling approach but the FPGAs start off into a
world of their own within their packages.
Jim Granville
Filled vias have an additional cost/risk, and BGAs are already a yield
hot spot.
What I have seen, is what I'd call tangent vias : these overlap the
pads, so that the hole is just under the solder mask. There is no trace.
Some CAD tools can also enable/disable Via sharing.
Sharing is good for packing more tracks in, but poor for lowest
impedance. ( fewer parallel paths result )
In extreme cases, more than one via could be beneficial, but that would
impact routing channels.
-jg
Jim Granville
> John_H wrote:
>>I've seen good information on Cadence tools based on Sun Microsystems work
>>that tracks what you've described with Ritchey. A recent Howard Johnson /
>>Xilinx talk also covered many of these items well without contradiction.
>
>
> The contradiction part I don't agree with. Many still argue that the
> distance between the IC and the cap is critical and some still say
> quantity is more important than variety of SRF.
It depends on the PCB topology:
For BGA, that is not true, as you (should) go the the plane first.
For 2 layer PCBs, with QFP packages, then the distance between cap and
IC is certainly critical :)
-jg
Symon
>
> I'm not sure what you are asking. A different capacitance will not
> change the inductive part of the impedance curve and a different
> inductance will not change the capacitive part of the curve. What
> changes in both cases is the SRF. So you put a few 0.1 uF caps on the
> board and a number more of 0.01 uF caps and even more of the 0.001 uF
> caps. Each capacitance value needs to have sufficient quantity to
> bring the impedance near the SRF low enough to be effective. Then the
> capacitive effect of the smaller caps keep the overall impedance low in
> spite of the larger caps being inductive. Finally the impedance of the
> ground planes keep the impedance low for the highest frequency. Doing
> a simulation is always a good thing to be able to see how the parallel
> resonances affect the impedance.
>
>
> distance between the IC and the cap is critical and some still say
> quantity is more important than variety of SRF. In one of these
> threads there was a link to a post by HJ. There were some things in
> the HJ post that were not supported by any sort of measurement or even
> simulation. I don't recall the details.
>
>
> the impedance low over the frequency range that matters to my design.
> The small deltas in inductance only move the SRF, they don't have a
> large impact on the impedance after you mix the capacitor values.
>
So, here's my thoughts.
If we have two caps of different values, but the same package/inductance,
there's a frequency between the SRF of the caps that has a parallel
resonance which leads to a peak in the impedance. For example, C1, a 1uF
0402 has a SRF of 10MHz. C2, a 0.1uF 0402 has a SRF of 25MHz. Between 10 MHz
and 25MHz, C1 looks inductive and C2 capacitive. This means there's a peak
in the impedance. So, the stragegy of using different values to 'even out'
the impedance gives us peaks (bad) and troughs (good) in the impedance
across the frequency spectrum.
However, for a 0.1uF 0402 cap, at resonance the ESR is 0.014R, so the Q of
the tuned circuit is about 5. For a 0402 1uF cap, the ESR at resonance is
0.01R, giving a Q of 2. These values of Q are so low as to make the self
resonance problem/advantage make bugger all difference. Note that a 10nF
0402 cap has a Q of about 3 at its SRF of 70MHz.
BTW, I got the cap data from here http://www.murata.com/designlib/mcsil.html
(Also, note that the vias/traces to connect these caps probably double the
inductance, reducing the SRF by 30%)
As for the 'plane capacitance', it starts to have an effect at frequencies >
1GHz which is a fat lot of good when our vias and BGA balls have inductances
in the nH region. Remember, we're not trying to bypass the power plane,
we're trying to bypass the IC.
In conclusion, mixing different values of ceramic caps in the same packages
might help a little but might hurt a little in a real system with FPGAs. I
maintain that using the biggest value in the size you choose is the best, if
nothing else because they have the crappest Q and this avoids BOM bloat. If
we do use a range, bully for us, we probably won't notice any difference,
but we have more chances for resonance and EMI failures.
Finally, I agree that the positioning of the cap is of lesser importance.
However, some of us prefer not to waste layers in our stacks on power
planes, we prefer to have decent grounds and route our FPGA power on layers
used for signals in other places. The HF plane capacitance is pissed away by
the chip mounting interconnect anyway, and its high Q might lead to evil
resonances. (As you mention in your posts, Rick.) In this case, with little
mini-planes for power routing, capacitor placement is crucial. (Note. With
FPGAs needing at least 3 supplies, and maybe a lot more, the PCBs are
getting very expensive with planes for every supply.)
In conclusion, for FPGA PCBs,
Lots of ground layers, one for every two signal layers.
One value of cap per size.
Use lots of caps. It means less impedance.
Power planes only need extend as far as the bypass caps. So, closer the caps
to the target device, the less plane needed.
IMHO, YMMV, HTH, Syms.
p.s. It's easy to simulate this stuff, try the excellent and free LTSpice
from
http://www.linear.com/company/software.jsp
(as recommended by Bob, thanks!)
p.p.s. Let me underline, _other_ways_work_too_ , but I'm happy with this
methodology, and I don't think other solutions work noticeable better.
Symon
news:44f4c58b$1...@x-privat.org...
>
> p.s. It's easy to simulate this stuff, try the excellent and free LTSpice
> from
> http://www.linear.com/company/software.jsp
> (as recommended by Bob, thanks!)
>
interesting to experiment and see where the resonances occur.
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fpga...@yahoo.com
rickman wrote:
> If nothing else you can check out the
> Ritchey book, "Right The First Time, A Practical Handbook on High Speed
> PCB and System Design, Volume 1". He is promising a Volume 2,
> "Included in this text will be a thorough treatment of EMI; a
> comprehensive description of the PCB fabrication process and PCB
> materials; a detailed examination of simulation tools and their use and
> a complete discussion of Gigabit and higher signaling protocols."
awesome ... thanks for the pointer ... ought to make some interesting
bed time reading ;)
Symon
values. The circuit sweeps from 5MHz to 45MHz back and forth. The first
three sweeps are done with two 1uF caps, the second three with a 1uF and a
0.1uF cap. Notice the big resonance at about 10MHz for the second set of
sweeps. The performance of the second circuit is slightly better at 45MHz,
worse at 5MHz, MUCH worse at 10MHz.
HTH, Syms.
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rickman
took. This information was presented in theory, demonstrated in
simulation and then proven with measurements.
Symon wrote:
> So, here's my thoughts.
>
> If we have two caps of different values, but the same package/inductance,
> there's a frequency between the SRF of the caps that has a parallel
> resonance which leads to a peak in the impedance. For example, C1, a 1uF
> 0402 has a SRF of 10MHz. C2, a 0.1uF 0402 has a SRF of 25MHz. Between 10 MHz
> and 25MHz, C1 looks inductive and C2 capacitive. This means there's a peak
> in the impedance. So, the stragegy of using different values to 'even out'
> the impedance gives us peaks (bad) and troughs (good) in the impedance
> across the frequency spectrum.
Having a peak is not bad if it is still below the max impedance you are
trying to achieve.
> However, for a 0.1uF 0402 cap, at resonance the ESR is 0.014R, so the Q of
> the tuned circuit is about 5. For a 0402 1uF cap, the ESR at resonance is
> 0.01R, giving a Q of 2. These values of Q are so low as to make the self
> resonance problem/advantage make bugger all difference. Note that a 10nF
> 0402 cap has a Q of about 3 at its SRF of 70MHz.
Yes, this is why you need to use lossy caps and not low ESR caps. This
is very important. But if you use just one value of cap such as 0.1
uF, you will likely see a much higher peak than you can tolerate. The
peak will be reduced by using more of them, or you can use a second or
third value of capacitance to end up with a series of closely spaced
peaks and troughs that are much lower than you will get with a single
value of cap. You can also use a lot fewer parts.
> BTW, I got the cap data from here http://www.murata.com/designlib/mcsil.html
>
> (Also, note that the vias/traces to connect these caps probably double the
> inductance, reducing the SRF by 30%)
You should have data to back this up, not speculation and BTW, what
traces? If you are connecting the caps with traces you have already
lost the battle. The experimental data shows the added inductance of
the via is not a significant factor in the overall picture when you use
multiple values to even out the inpedance over frequency.
> As for the 'plane capacitance', it starts to have an effect at frequencies >
> 1GHz which is a fat lot of good when our vias and BGA balls have inductances
> in the nH region. Remember, we're not trying to bypass the power plane,
> we're trying to bypass the IC.
Again you should have data on hand before you speculate. In the
Ritchey book data is provided to show that the impedance of a closely
spaced power/ground plane pair is lower than the typical capacitors
around 100 MHz. Of course this depends on the size and construction of
the board. But clearly the region of importance is much lower than 1
GHz.
In addition, the impedance of your package leads has no bearing on the
power decoupling. No amount of capacitace external or internal to the
device will have any impact on the bounce that will be caused by power
lead inductance. The only cure for that is a new package.
> In conclusion, mixing different values of ceramic caps in the same packages
> might help a little but might hurt a little in a real system with FPGAs. I
> maintain that using the biggest value in the size you choose is the best, if
> nothing else because they have the crappest Q and this avoids BOM bloat. If
> we do use a range, bully for us, we probably won't notice any difference,
> but we have more chances for resonance and EMI failures.
This is not borne out by the facts. If you can get your hands on
Richey's book I would suggest that it is a valuable addition to any
library on SI and EMI. His volume 2 will cover EMI in more detail and
I am looking forward to it.
> Finally, I agree that the positioning of the cap is of lesser importance.
> However, some of us prefer not to waste layers in our stacks on power
> planes, we prefer to have decent grounds and route our FPGA power on layers
> used for signals in other places. The HF plane capacitance is pissed away by
> the chip mounting interconnect anyway, and its high Q might lead to evil
> resonances. (As you mention in your posts, Rick.) In this case, with little
> mini-planes for power routing, capacitor placement is crucial. (Note. With
> FPGAs needing at least 3 supplies, and maybe a lot more, the PCBs are
> getting very expensive with planes for every supply.)
Wow! If your design is not high speed and the edge rates are not very
fast, then power distribution is not a big deal. But nearly everything
in this paragraph is incorrect. Yes, power planes cost money, that is
true. Now that I understand how simple it is to figure out how power
distribution works, I would never use any of these ideas on a board
where I needed good noise margin or had high speed signals.
BTW, I never said a high Q power plane pair is bad. Yes, it can create
impedance holes at very high frequencies, but the alternative for your
approach would raise the floor, not lower the ceiling.
> In conclusion, for FPGA PCBs,
> Lots of ground layers, one for every two signal layers.
> One value of cap per size.
> Use lots of caps. It means less impedance.
> Power planes only need extend as far as the bypass caps. So, closer the caps
> to the target device, the less plane needed.
>
> IMHO, YMMV, HTH, Syms.
>
> p.s. It's easy to simulate this stuff, try the excellent and free LTSpice
> from
> http://www.linear.com/company/software.jsp
> (as recommended by Bob, thanks!)
> p.p.s. Let me underline, _other_ways_work_too_ , but I'm happy with this
> methodology, and I don't think other solutions work noticeable better.
Have you tried simulating any of this? I would like to know what
results your methods produce. The question is not so much if a method
has worked a few times for you, but do you *know* it is going to work
before you build the board. Ritchey's method lets you *know* it will
work right the first time.
rickman
code you posted. But this simulation is not of a power distribution
system. Try adding a power plane and just one value of cap (the 0.1uF
is what you suggested IIRC) and simulate up to 200 MHz or so. I think
you will find that you get a *huge* parallel resonance peak from the
two. If you add a few 0.01 uF caps this peak will be split in two and
the highest will be much smaller. Then add a few more 0.001 uF caps
and you will see the peaks reduced further. It also helps if you use
caps with a low Q factor or high ESR (relatively speaking). But then
at 0.1 uF, I don't think you will find a C0G so X7R should be fine.
Symon wrote:
> OK, here's a LTSpice file that shows a resonance between disimilar cap
> values. The circuit sweeps from 5MHz to 45MHz back and forth. The first
> three sweeps are done with two 1uF caps, the second three with a 1uF and a
> 0.1uF cap. Notice the big resonance at about 10MHz for the second set of
> sweeps. The performance of the second circuit is slightly better at 45MHz,
> worse at 5MHz, MUCH worse at 10MHz.
> HTH, Syms.
>
> Version 4
> SHEET 1 1516 904
> WIRE 1040 432 800 432
....snip...
Symon
> Most of what you said goes against what was taught in the class I just
> took. This information was presented in theory, demonstrated in
> simulation and then proven with measurements.
>
>
> Symon wrote:
> > So, here's my thoughts.
> >
> > If we have two caps of different values, but the same
package/inductance,
> > there's a frequency between the SRF of the caps that has a parallel
> > resonance which leads to a peak in the impedance. For example, C1, a 1uF
> > 0402 has a SRF of 10MHz. C2, a 0.1uF 0402 has a SRF of 25MHz. Between 10
MHz
> > and 25MHz, C1 looks inductive and C2 capacitive. This means there's a
peak
> > in the impedance. So, the stragegy of using different values to 'even
out'
> > the impedance gives us peaks (bad) and troughs (good) in the impedance
> > across the frequency spectrum.
>
> Having a peak is not bad if it is still below the max impedance you are
> trying to achieve.
>
>
> > However, for a 0.1uF 0402 cap, at resonance the ESR is 0.014R, so the Q
of
> > the tuned circuit is about 5. For a 0402 1uF cap, the ESR at resonance
is
> > 0.01R, giving a Q of 2. These values of Q are so low as to make the self
> > resonance problem/advantage make bugger all difference. Note that a 10nF
> > 0402 cap has a Q of about 3 at its SRF of 70MHz.
>
> Yes, this is why you need to use lossy caps and not low ESR caps. This
> is very important. But if you use just one value of cap such as 0.1
> uF, you will likely see a much higher peak than you can tolerate. The
> peak will be reduced by using more of them, or you can use a second or
> third value of capacitance to end up with a series of closely spaced
> peaks and troughs that are much lower than you will get with a single
> value of cap. You can also use a lot fewer parts.
>
> > BTW, I got the cap data from here
http://www.murata.com/designlib/mcsil.html
> >
> > (Also, note that the vias/traces to connect these caps probably double
the
> > inductance, reducing the SRF by 30%)
>
> You should have data to back this up, not speculation and BTW, what
> traces? If you are connecting the caps with traces you have already
> lost the battle. The experimental data shows the added inductance of
> the via is not a significant factor in the overall picture when you use
> multiple values to even out the inpedance over frequency.
>
speculation. And no, you haven't lost the battle with a few tiny traces, the
vias are the bad guys as they give you loop area.
>
> > As for the 'plane capacitance', it starts to have an effect at
frequencies >
> > 1GHz which is a fat lot of good when our vias and BGA balls have
inductances
> > in the nH region. Remember, we're not trying to bypass the power plane,
> > we're trying to bypass the IC.
>
> Again you should have data on hand before you speculate. In the
> Ritchey book data is provided to show that the impedance of a closely
> spaced power/ground plane pair is lower than the typical capacitors
> around 100 MHz. Of course this depends on the size and construction of
> the board. But clearly the region of importance is much lower than 1
> GHz.
>
> In addition, the impedance of your package leads has no bearing on the
> power decoupling. No amount of capacitace external or internal to the
> device will have any impact on the bounce that will be caused by power
> lead inductance. The only cure for that is a new package.
>
this has on the IC? Why would you go to all that effort if the package
you're stuck with prevents your efforts making any difference?
>
> > In conclusion, mixing different values of ceramic caps in the same
packages
> > might help a little but might hurt a little in a real system with FPGAs.
I
> > maintain that using the biggest value in the size you choose is the
best, if
> > nothing else because they have the crappest Q and this avoids BOM bloat.
If
> > we do use a range, bully for us, we probably won't notice any
difference,
> > but we have more chances for resonance and EMI failures.
>
> This is not borne out by the facts. If you can get your hands on
> Richey's book I would suggest that it is a valuable addition to any
> library on SI and EMI. His volume 2 will cover EMI in more detail and
> I am looking forward to it.
>
>
> > Finally, I agree that the positioning of the cap is of lesser
importance.
> > However, some of us prefer not to waste layers in our stacks on power
> > planes, we prefer to have decent grounds and route our FPGA power on
layers
> > used for signals in other places. The HF plane capacitance is pissed
away by
> > the chip mounting interconnect anyway, and its high Q might lead to evil
> > resonances. (As you mention in your posts, Rick.) In this case, with
little
> > mini-planes for power routing, capacitor placement is crucial. (Note.
With
> > FPGAs needing at least 3 supplies, and maybe a lot more, the PCBs are
> > getting very expensive with planes for every supply.)
>
> Wow! If your design is not high speed and the edge rates are not very
> fast, then power distribution is not a big deal. But nearly everything
> in this paragraph is incorrect. Yes, power planes cost money, that is
> true. Now that I understand how simple it is to figure out how power
> distribution works, I would never use any of these ideas on a board
> where I needed good noise margin or had high speed signals.
>
package connections are having on the PDS design. As I said, the whole point
of the exercise is to get good supplies on the IC, not the power plane. The
plane capacitance has such high Q it's good to severel GHz, I reiterate that
you can't benefit from this on the device. I suggest you look at how Xilinx
themselves route the power to their Rocket I/Os on their demo boards. The
power supplies aren't on planes. The connection between the PCB and the IC
mean it's a waste of time, I suspect for these Gbit circuits they embed caps
on the FBGA.
>
> BTW, I never said a high Q power plane pair is bad. Yes, it can create
> impedance holes at very high frequencies, but the alternative for your
> approach would raise the floor, not lower the ceiling.
>
THE SILICON. You've gotta get that HF energy through vias, bga balls,
traces(maybe) to the device.
>
> > In conclusion, for FPGA PCBs,
> > Lots of ground layers, one for every two signal layers.
> > One value of cap per size.
> > Use lots of caps. It means less impedance.
> > Power planes only need extend as far as the bypass caps. So, closer the
caps
> > to the target device, the less plane needed.
> >
> > IMHO, YMMV, HTH, Syms.
> >
> > p.s. It's easy to simulate this stuff, try the excellent and free
LTSpice
> > from
> > http://www.linear.com/company/software.jsp
> > (as recommended by Bob, thanks!)
> > p.p.s. Let me underline, _other_ways_work_too_ , but I'm happy with this
> > methodology, and I don't think other solutions work noticeable better.
>
> Have you tried simulating any of this? I would like to know what
> results your methods produce. The question is not so much if a method
> has worked a few times for you, but do you *know* it is going to work
> before you build the board. Ritchey's method lets you *know* it will
> work right the first time.
>
simulations. So, take a look at my LTSpice sim posts.
HTH, Syms.
Symon
website and learn how to simulate what you suggest? Then you can prove stuff
to yourself without having to go to expensive classes. :-) You might even
want to simulate the stuff you learned at your class with a real world
situation and see how much benefit you get. Let us know how you get on.
Good luck, Syms.
Symon
to 200MHz with a 100pF plane and two combinations of bypass capacitors. (Cap
data here:- http://www.murata.com/designlib/mcsil.html )
If there's anyone out there who has both the time and ability to run a
simulation, I'd appreciate some thoughts as to why my simulation doesn't
match up with Rick's classes. I'm trying to find a *huge* parallel
resonance! :-) I'm also looking for the benefits of different valued caps,
as opposed to just using the biggest value you can get in the package you
use.
Thanks, Syms.
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Symon
> So, here's a LTSpice ( http://www.linear.com/company/software.jsp ) SIM up
> to 200MHz with a 100pF plane and two combinations of bypass capacitors.
(Cap
> data here:- http://www.murata.com/designlib/mcsil.html )
>
> If there's anyone out there who has both the time and ability to run a
> simulation, I'd appreciate some thoughts as to why my simulation doesn't
> match up with Rick's classes. I'm trying to find a *huge* parallel
> resonance! :-) I'm also looking for the benefits of different valued caps,
> as opposed to just using the biggest value you can get in the package you
> use.
> Thanks, Syms.
>
>
caps. The resonance went away once I put a decent number of caps in the
circuit. Who has only 4 caps on a board 30cm by 20cm? I'm still looking for
a design where mixing the caps is better than not.
Cheers, Syms.
fpga...@yahoo.com
rickman wrote:
> In addition, the impedance of your package leads has no bearing on the
> power decoupling. No amount of capacitace external or internal to the
> device will have any impact on the bounce that will be caused by power
> lead inductance. The only cure for that is a new package.
I pretty much came to this realization with the XCV2000E parts in the
BG560 package for high density reconfigurable computing needs. There
was nothing I could do to overcome the BG560 packages small via, trace
and bonding wire inductance to make the parts stable. Only choice was
to seriously derate them.
David Brown
> John_H wrote:
>> "rickman" <gnu...@gmail.com> wrote in message
>> Won't any higher inductance result in the same above-SRF slope? That is,
>> given the total inductance, it won't matter what the capacitance is once
>> above an ohm in the impedance vs freq plot.
>
> I'm not sure what you are asking. A different capacitance will not
> change the inductive part of the impedance curve and a different
> inductance will not change the capacitive part of the curve. What
> changes in both cases is the SRF. So you put a few 0.1 uF caps on the
> board and a number more of 0.01 uF caps and even more of the 0.001 uF
> caps. Each capacitance value needs to have sufficient quantity to
> bring the impedance near the SRF low enough to be effective. Then the
> capacitive effect of the smaller caps keep the overall impedance low in
> spite of the larger caps being inductive. Finally the impedance of the
> ground planes keep the impedance low for the highest frequency. Doing
> a simulation is always a good thing to be able to see how the parallel
> resonances affect the impedance.
>
I've not any high speed boards - the last board I made had internal
frequencies at 150 MHz, and an external bus at 75 MHz (overclocked in
testing to about 240/120 MHz), so maybe I'm missing something that
happens at higher frequencies.
Using a simple tool such as Murata's software, I looked at the
impedances for different capacitors at different frequencies. To a fair
extent, the inductance is determined by the package size (and the board
vias and traces), while the capacitance obviously goes up with the cap's
value. So choosing a 0.01 uF instead of a 0.1 uF cap increases the
capacitance side of the impedance curve by a factor of 10, and leaves
the inductive side unchanged. It changes the peak frequency, but I fail
to see why that should make a real difference - it has the same or
higher impedance across the frequency range. Given that the 0.1 uF type
has lower ESR (being made of more parallel plates), I can't find any way
in which the 0.01 uF is better. So as Symon says (unless I'm
misinterpreting him), the best arrangement is to pick the smallest size
package you can conveniently mount (0603 for us), then the largest
capacitance value you can conveniently and economically get in that size
(100 nF), and use as many as needed for the board. Placement should be
close to the device where possible, but is not very critical as long as
it is within the range of the mini power plane (i.e., polygon on a
signal layer).
It works for me - but then again, I'm not doing really high-end cards.
rickman
> > trying to achieve.
> >
> But it's better not to have it, right?
Better than what? If it meets your requirements, then you are done.
> So, you loaded up the LTSpice simulations I posted, right? That's not
> speculation. And no, you haven't lost the battle with a few tiny traces, the
> vias are the bad guys as they give you loop area.
Your simulation was for two caps with no power plane, right? That is
not a useful simulation.
> So, you advocate decoupling the power plane without considering what effect
> this has on the IC? Why would you go to all that effort if the package
> you're stuck with prevents your efforts making any difference?
A quiet plane is part of the solution. If your package produces ground
bounce that blows your noise budget, you have no hope of building a
good design. If so, you need to get a part with a better package. I
don't get what you are saying.
> > This is not borne out by the facts. If you can get your hands on
> > Richey's book I would suggest that it is a valuable addition to any
> > library on SI and EMI. His volume 2 will cover EMI in more detail and
> > I am looking forward to it.
> >
> I have different facts, look at the sims I posted.
Ok, is this conversation coming to an end? I don't want to argue about
this. Your simulation was for two capacitors if I understood
correctly. That has no bearing on the problem of power plane
decoupling. Without simulating the power planes you aren't simulating
anything useful.
> > Wow! If your design is not high speed and the edge rates are not very
> > fast, then power distribution is not a big deal. But nearly everything
> > in this paragraph is incorrect. Yes, power planes cost money, that is
> > true. Now that I understand how simple it is to figure out how power
> > distribution works, I would never use any of these ideas on a board
> > where I needed good noise margin or had high speed signals.
> >
> I see from this paragraph you may not have grasped the effect that the BGA
> package connections are having on the PDS design. As I said, the whole point
> of the exercise is to get good supplies on the IC, not the power plane. The
> plane capacitance has such high Q it's good to severel GHz, I reiterate that
> you can't benefit from this on the device. I suggest you look at how Xilinx
> themselves route the power to their Rocket I/Os on their demo boards. The
> power supplies aren't on planes. The connection between the PCB and the IC
> mean it's a waste of time, I suspect for these Gbit circuits they embed caps
> on the FBGA.
Yes, you need to consider the package inductance. But you can't expect
the power plane to fix a problem with the package. You can analyze
them separately. The power plane will have noise from the effects of
all chips on the board. The chip package inductance will only affect
that one part. So analyze how much noise each will contribute and do
what it takes to stay within your noise margin. Beyond that it is not
useful to analyze them together.
> > BTW, I never said a high Q power plane pair is bad. Yes, it can create
> > impedance holes at very high frequencies, but the alternative for your
> > approach would raise the floor, not lower the ceiling.
> >
> I'm not saying it's necessarily bad. But it's not a great deal of help ON
> THE SILICON. You've gotta get that HF energy through vias, bga balls,
> traces(maybe) to the device.
Any noise you have on the power planes will add to the noise that the
silicon sees.
> Only a nutter would do this without thinking about it and running some
> simulations. So, take a look at my LTSpice sim posts.
Are you thinking of simulating with the power planes?
rickman
I will be doing that when I am ready to layout my next board.
rickman
> I've not any high speed boards - the last board I made had internal
> frequencies at 150 MHz, and an external bus at 75 MHz (overclocked in
> testing to about 240/120 MHz), so maybe I'm missing something that
> happens at higher frequencies.
>
> Using a simple tool such as Murata's software, I looked at the
> impedances for different capacitors at different frequencies. To a fair
> extent, the inductance is determined by the package size (and the board
> vias and traces), while the capacitance obviously goes up with the cap's
> value. So choosing a 0.01 uF instead of a 0.1 uF cap increases the
> capacitance side of the impedance curve by a factor of 10, and leaves
> the inductive side unchanged. It changes the peak frequency, but I fail
> to see why that should make a real difference - it has the same or
> higher impedance across the frequency range. Given that the 0.1 uF type
> has lower ESR (being made of more parallel plates), I can't find any way
> in which the 0.01 uF is better. So as Symon says (unless I'm
> misinterpreting him), the best arrangement is to pick the smallest size
> package you can conveniently mount (0603 for us), then the largest
> capacitance value you can conveniently and economically get in that size
> (100 nF), and use as many as needed for the board. Placement should be
> close to the device where possible, but is not very critical as long as
> it is within the range of the mini power plane (i.e., polygon on a
> signal layer).
>
> It works for me - but then again, I'm not doing really high-end cards.
The amount of decoupling required is not a function of the clock rate.
It depends on the slew rate of your signals and the length of the
transmission lines. The length determines the lower frequencies you
will need to decouple and the slew rate determines the highest
frequencies. Of course there are other aspects that you need to
decouple, such as switching inside the chips. For that you need to
compare the maximum transition in current the chip will produce to the
maximum noise voltage you can tolerate. Then use the resulting
impedance as the goal for decoupling.
Ritchey's data was very clear on this. Adding a single value of caps
to a power plane produced a resonance with a higher impedance than that
of the plane alone over a significant frequency range. By using
multiple cap values he was able to decouple a board with just a
handfull of caps rather than the mountain that are normally used. Most
importantly, he could show that his decoupling design worked correctly
before he built the board rather than verifying it in testing.
I wish I could post the images from Ritchey's book. I have tried to
describe his measurements in detail, but a picture is worth a thousand
words (or maybe more). Moving the SRF is what makes it work. If you
use a hundred 0.1 uF caps you should get a parallel resonant peak in
impedance as the capacitor resonates with the power plane. Assuming
the capacitor has a high Q, then no number of capacitors will
significantly reduce that peak. Of course the caps don't have a high Q
so some number of caps *will* reduce the peak to an acceptable level.
Or you can add a smaller number of caps with a smaller value. These
caps will produce a higher frequency resonance with the power plane.
You can then add a third value of cap to move that resonance higher.
Each time you add a value of cap you flatten the impedance curve. If
the caps are not high Q, by the time you have added 0.1, 0.01 and 0.001
caps you will have flattened it enough to not see any real peaks, but
rather just ripple in the frequency response. This will take a lot
fewer caps than the hundreds that are often used on boards, even at the
frequencies you are using.
Or think of it from the other direction. You add the 0.001 uF caps to
decouple the plane at the highest frequencies that caps can be
effective. But they don't work well at lower frequencies so add a
smaller number of 0.01 uF caps to provide decoupling at a lower
frequency. Then add just a small number of 0.1 uF caps for the lower
freqs and so on down to the tantalum caps for bulk at the lowest
frequencies until the PSU response time can adequately maintain the
voltage.
David Brown
Thanks for taking the time explaining this - between you and Symon I'm
hopefully learning something!
However, I've a couple of issues here. First off, I can't see that the
power planes have much capacitive effect at these frequencies (the
"planes" being polygons, with other signals on the same layer, and thus
having plenty of gaps). But I'll happily admit to not having a clear
idea how to model such planes or polygons.
Secondly, I understand about different caps working better at different
frequencies, and obviously have bulk capacitors for the lower
frequencies (electrolytics near the regulators, and a few 4.7uF ceramics
around the board). But I still can't find any reason to expect a 0.001
uF ceramic 0603 capacitor to be significantly better at higher
frequencies than a 0.1 uF ceramic (same dialectric) 0603 capacitor.
Using the muRata software, I picked a 0603 X7R 100 nF capacitor. The
software gives it an SRF of 21 MHz, L of 0.63 nH, R of 0.027 O, and an
impedance of 0.14 ohm at 10 MHz, 0.02 ohm at 20 MHz, 0.16 ohm at 50 MHz,
0.38 ohm at 100 MHz, 0.78 at 200 MHz, and 1.97 ohm at 500 MHz. Picking
a 10 nF cap with the same setup gives an SFR of 67 MHz, and impedances
at these frequencies of 1.66, 0.77, 0.16, 0.24, 0.71 and 1.95 ohms. In
other words, it is a better at around 100 MHz, but not vastly better.
Until we start looking at special 0306 caps for frequencies of several
hundred MHz, I just don't see the benefit of smaller capacitance values.
Even then, it is more economical to simply use a few extra caps of the
same type (assuming the board has space for it).
It doesn't even take that many caps - I've got about a dozen for the
processor (which as two main supplies and a PLL supply), two or three
for each of the sdram chips, and one or two for each of the other major
chips.
One thing that makes a significant difference is that I'm not driving
any fast, high current lines - signalling is (almost) all TTL levels.
Higher current drives would mean more capacitors, but I'd still expect
to use the same types.
Symon
> Symon wrote:
> > So, you advocate decoupling the power plane without considering what
effect
> > this has on the IC? Why would you go to all that effort if the package
> > you're stuck with prevents your efforts making any difference?
>
> A quiet plane is part of the solution. If your package produces ground
> bounce that blows your noise budget, you have no hope of building a
> good design. If so, you need to get a part with a better package. I
> don't get what you are saying.
>
OK, I think you're correct, this conversation has reached an end. It can go
nowhere with one of us posting data and sims (including ones that model the
power planes, albeit as a lumped capacitance) that the other cannot or will
not look at, the other posting hearsay from a class he went to. I will,
however, try to make one last point based on the snippet above.
I contend that the package impedance of modern FPGAs is such that any
benefit that a board wide power plane's capacitance could provide to your
design, over and above that which you can get from a small local plane and
associated bypass capacitors, is negligible. The caps work up to a few
hundred MHz, just about where the package stops working. Any noise on the
supply above this frequency doesn't get to the silicon anyway.
As posting a simulation to show this is wasted effort, I instead refer you
to UG076, Figure 6-3, which shows how Xilinx power their Rocket-IO
circuitry. I also offer
http://www.eetasia.com/ARTICLES/2006MAY/PDF/EEOL_2006MAY16_POW_EMD_TA.pdf
as further reading.
Thanks for encouraging me to simulate this stuff again, it's given me some
more ideas for my next layout! I'm also gladdened that, as you mention in
one of your posts, you will be simulating your next board. If you are able
to share your results, I for one would be most interested to see them.
Yours &c, Syms.
rickman
> Thanks for taking the time explaining this - between you and Symon I'm
> hopefully learning something!
I had written a reply to this post, but I hit a wrong button as I typed
and POOF! So here it is again...
> However, I've a couple of issues here. First off, I can't see that the
> power planes have much capacitive effect at these frequencies (the
> "planes" being polygons, with other signals on the same layer, and thus
> having plenty of gaps). But I'll happily admit to not having a clear
> idea how to model such planes or polygons.
If your planes are not designed to have good capacitance, then they
won't. They need to be complete on thier own layer and closely spaced.
It is not hard to get nFs from planes with very low inductance.
> Secondly, I understand about different caps working better at different
> frequencies, and obviously have bulk capacitors for the lower
> frequencies (electrolytics near the regulators, and a few 4.7uF ceramics
> around the board). But I still can't find any reason to expect a 0.001
> uF ceramic 0603 capacitor to be significantly better at higher
> frequencies than a 0.1 uF ceramic (same dialectric) 0603 capacitor.
It is not just that the caps work at different frequencies, it is how
they work with the power planes. A cap closely coupled to the power
planes will have a resonance (or anti-resonance) which will create a
*higher* impedance in that range of frequencies than either the cap or
plane alone. If you pick a cap of small value and low Q (high ESR) it
will have a low amplitude resonance, high in frequency. This same cap
will require a lot of them to provide effective coupling at lower
frequencies. So you can then use a smaller number of larger value caps
to provide a lowered impedance at lower frequencies. Again it is
important to not use parts with a high Q as this will raise the
amplitude of the impedance peaks due to parallel resonance. By using a
range of cap values the impedance is kept low across a wide range of
frequency and the resonances are kept to a minimum.
> Using the muRata software, I picked a 0603 X7R 100 nF capacitor. The
> software gives it an SRF of 21 MHz, L of 0.63 nH, R of 0.027 O, and an
> impedance of 0.14 ohm at 10 MHz, 0.02 ohm at 20 MHz, 0.16 ohm at 50 MHz,
> 0.38 ohm at 100 MHz, 0.78 at 200 MHz, and 1.97 ohm at 500 MHz. Picking
> a 10 nF cap with the same setup gives an SFR of 67 MHz, and impedances
> at these frequencies of 1.66, 0.77, 0.16, 0.24, 0.71 and 1.95 ohms. In
> other words, it is a better at around 100 MHz, but not vastly better.
> Until we start looking at special 0306 caps for frequencies of several
> hundred MHz, I just don't see the benefit of smaller capacitance values.
> Even then, it is more economical to simply use a few extra caps of the
> same type (assuming the board has space for it).
But this does not take the parallel resonance into account. If
parallel resonance did not matter we could decouple everything with a
few tantalum caps.
> It doesn't even take that many caps - I've got about a dozen for the
> processor (which as two main supplies and a PLL supply), two or three
> for each of the sdram chips, and one or two for each of the other major
> chips.
It sounds like this is a simple design, but have you tested worse case?
Try the situation where the address and data bus both change from all
0s to all 1s at the same moment (assuming this processor can do that).
The DSP I last designed with would switch both data and address busses
at the same time. Put a high speed scope probe (with a very short
ground) on a separate output from this part that is set to a 1 and
watch the glitch, that is your total bounce including the inductance
from the power pins and the plane bounce. Also measure the glitch on a
power pin and you will have just the power plane noise. After you
consider this noise and the other sources such as crosstalk, can you
tell if your design is quiet enough. Testing won't do it unless you
explicitly test your worst cases.
> One thing that makes a significant difference is that I'm not driving
> any fast, high current lines - signalling is (almost) all TTL levels.
> Higher current drives would mean more capacitors, but I'd still expect
> to use the same types.
If you are driving with fast edges, you are driving high current.
Series terminated 3.3 volt CMOS driving a 50 ohm transmission line will
drive 33 mA per line. It will be much higher if it is not series
terminated. Multiply that by 64 and you get 2 Amps! Did you consider
this much current in your decoupling calculations? If you don't supply
the current from the power plane the caps can't really keep up with the
fast rise time of many drivers (< 1 ns). It will create high noise on
the planes and can trigger bounce logic level problems.
If you are using an MCU with fully internal memory then we are talking
about a different class of design and you can get by with a dozen or so
of single value caps.
fpga...@yahoo.com
Symon wrote:
> OK, I think you're correct, this conversation has reached an end. It can go
> nowhere with one of us posting data and sims (including ones that model the
> power planes, albeit as a lumped capacitance) that the other cannot or will
> not look at, the other posting hearsay from a class he went to. I will,
> however, try to make one last point based on the snippet above.
Probably, but I also think this topic should probably be revisited from
time to time as well. As Austin stated in the intro post, there are few
reasons to stack caps (unless the dominant cause is lack of adequate
capacitance), which simply shouldn't happen if you have a good idea
what worst case current spikes from the chip are. That unfortunately
isn't specified, because it's highly variable depending on the design,
place/route, and other factors. If something is "fixed" by adding some
additional medium/low speed capacitance, then you made some wrong
assumption, or have a process problem (like poor via plating as I've
seen before).
My experience is that there are some designs, which do not work in some
packages, even with best possible practice on the user PCB, simply
because of the inductance and resistances in the package. My REALLY BAD
experience was XCV2000E's in BG560's. I've had similar problems with
other parts that are not nearly as clear, but find comfort that Xilinx
is improving packaging so they believe that XC4V and XC5V should not be
a problem. When I have time, I may revisit the PCB layouts given your
wonderful enlightment, and see if there are improvements to be made.
Maybe I'll even risk getting a few XC4VLX100, XC4VLX200's, or XC5V
parts and giving it a try. I suspect there may still be some land mines
that are related to very dense designs which are optimized to one
combinatorial delay based around SRL's, with minimum inter LUT routing
dominating the timing and power requirements, and may result in very
short power bursts several times the average current. In the largest
parts, the clock skew may hide this, thus preventing the current
stackup. If it's possible to juggle the routing to balance the clock
skew, there may well still be "perverse" ways of getting the parts to
fail, that can also be accidentally invoked by placement and routing
variations. It would be interesting to spend a few days to verify this,
and see if it really is safe not to worry about unexpected worst case
stackups.
In the end, we may have to move to the next level, and get rid of the
packages all togather. When I asked Xilinx about getting raw tested die
for direct user PCB attach last year they were a very resistant. With
half, or better of the inductance still remaining in the package, it's
getting tougher, even with best practice, to meet the demands for high
performance applications.
thanks .. and Have Fun!!
John
Symon
news:44f59085$1...@news.wineasy.se...
I think the main issue at stake in this thread isn't the impedances per se,
but resonances between the various components of the board assembly. I
recommend that you try using spice simulations to see these resonance
mechanisms for yourself. This certainly increased my understanding of the
subject. The LTSpice files I posted might help get you started.
In summary, I think we have (at least) two different methodologies in this
thread.
1) Rick's teacher has presented a way to prevent resonances between bypass
caps and power planes. These resonances can be substantial because of the
high Q of the plane capacitance. He prevents this serious resonance by using
a bunch of different valued capacitors to move and spread out the resonance.
This introduces new parallel resonances between these different valued caps,
but these aren't as bad as the original plane resonance because the caps
have low Q.
2) For FPGA boards, I suggest a solution whereby we dispense with the power
plane. Hence no serious resonance, as we have no high Q components. Use one
value of decoupling cap to prevent resonances between different values. Pick
a value with crappy Q. We have lost the very high frequency decoupling
capability of the plane capacitance, but that was no use anyway as we can't
couple this plane capacitance to the device we're using because its package
has too much inductance (from its balls and vias plus the PCB vias).
Instead, we use a bunch (maybe even a bigger bunch than in (1)) of bypass
caps (very) near the device and a small 'mini-plane' to parallel them
together. The money you've saved by removing a PCB layer pays for the extra
caps.
Both methods will work. Each has pros and cons. But I use methodology 2).
:-) As package technology advances, I will re-evaluate this position. I may
also need to learn how to use a 3-D modelling package, as lumped simulation
is not much help beyond 1GHz.
Cheers, Syms.
p.s. In both methods, the over-riding key issue is to have a decent ground.
Without that, forget everything.
fpga...@yahoo.com
Martin Thompson
> I contend that the package impedance of modern FPGAs is such that any
> benefit that a board wide power plane's capacitance could provide to your
> design, over and above that which you can get from a small local plane and
> associated bypass capacitors, is negligible. The caps work up to a few
> hundred MHz, just about where the package stops working. Any noise on the
> supply above this frequency doesn't get to the silicon anyway.
I'll chip in one more point (which I have not data for, but discussion
may be enlightening :-)..
Even above the frequency at which the die won't see the noise due to
the package inductance, the noise on the planes may still cause
problems in passing EMC emissions tests, so you still have to be
careful at the top end.
Out of interest - do you consider how your mini-planes resonate at
high frequencies?
Cheers,
Martin
--
martin.j...@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
David Brown
I'm now beginning to get a better idea of the parallel resonance
problem. In particular, it's the high Q of the plane capacitor that
causes the biggest issue.
>
>> Using the muRata software, I picked a 0603 X7R 100 nF capacitor. The
>> software gives it an SRF of 21 MHz, L of 0.63 nH, R of 0.027 O, and an
>> impedance of 0.14 ohm at 10 MHz, 0.02 ohm at 20 MHz, 0.16 ohm at 50 MHz,
>> 0.38 ohm at 100 MHz, 0.78 at 200 MHz, and 1.97 ohm at 500 MHz. Picking
>> a 10 nF cap with the same setup gives an SFR of 67 MHz, and impedances
>> at these frequencies of 1.66, 0.77, 0.16, 0.24, 0.71 and 1.95 ohms. In
>> other words, it is a better at around 100 MHz, but not vastly better.
>> Until we start looking at special 0306 caps for frequencies of several
>> hundred MHz, I just don't see the benefit of smaller capacitance values.
>> Even then, it is more economical to simply use a few extra caps of the
>> same type (assuming the board has space for it).
>
> But this does not take the parallel resonance into account. If
> parallel resonance did not matter we could decouple everything with a
> few tantalum caps.
>
You're right - I've been looking at the capacitors separately rather
than how they affect each other.
The card is not nearly as advanced as many of the cards made by people
in this group - it's highest frequencies are in the 150 MHz range, with
relatively few fast traces (there is a databus to an sdram chip, but the
only lines I really have to be careful with are the clocks to the sdram
chips at 75 MHz), and everything is fairly low power.
What you (and Symon) have given me is a number of ideas about the
problems on higher speed cards, and possible solutions to the problems,
along with a better understanding of what I don't know and need to learn
about if I am ever involved in making faster cards. I'm not a
specialist in this field (I'm mainly an embedded programmer), and know
that cards using the bigger and faster FPGAs would be completely out of
my depth, but I appreciate the tips I pick up here for my cards anyway.
>
>> It doesn't even take that many caps - I've got about a dozen for the
>> processor (which as two main supplies and a PLL supply), two or three
>> for each of the sdram chips, and one or two for each of the other major
>> chips.
>
> It sounds like this is a simple design, but have you tested worse case?
> Try the situation where the address and data bus both change from all
> 0s to all 1s at the same moment (assuming this processor can do that).
> The DSP I last designed with would switch both data and address busses
> at the same time. Put a high speed scope probe (with a very short
> ground) on a separate output from this part that is set to a 1 and
> watch the glitch, that is your total bounce including the inductance
> from the power pins and the plane bounce. Also measure the glitch on a
> power pin and you will have just the power plane noise. After you
> consider this noise and the other sources such as crosstalk, can you
> tell if your design is quiet enough. Testing won't do it unless you
> explicitly test your worst cases.
>
I've done some worst-case (or close to worst case) testing of the
databus, but it would probably be a good idea to do some better
measurements during such tests.
>
>> One thing that makes a significant difference is that I'm not driving
>> any fast, high current lines - signalling is (almost) all TTL levels.
>> Higher current drives would mean more capacitors, but I'd still expect
>> to use the same types.
>
> If you are driving with fast edges, you are driving high current.
> Series terminated 3.3 volt CMOS driving a 50 ohm transmission line will
> drive 33 mA per line. It will be much higher if it is not series
> terminated. Multiply that by 64 and you get 2 Amps! Did you consider
> this much current in your decoupling calculations? If you don't supply
> the current from the power plane the caps can't really keep up with the
> fast rise time of many drivers (< 1 ns). It will create high noise on
> the planes and can trigger bounce logic level problems.
>
I've done some rough calculations, but the drivers are not that fast -
although I appreciate the levels of the current spikes. I have not seen
any indications of noise problems or bounce, but perhaps I need to do
some more careful measurements.
> If you are using an MCU with fully internal memory then we are talking
> about a different class of design and you can get by with a dozen or so
> of single value caps.
>
The memory is not internal on this MCU, but I agree it's a different
class to designs using much higher speed devices and signals. I'm not
overly concerned about this design, but perhaps future cards will have
DDR memory and need more care.
al82
Symon ha escrito:
>
> 1) Rick's teacher has presented a way to prevent resonances between bypass
> caps and power planes. These resonances can be substantial because of the
> high Q of the plane capacitance. He prevents this serious resonance by using
> a bunch of different valued capacitors to move and spread out the resonance.
> This introduces new parallel resonances between these different valued caps,
> but these aren't as bad as the original plane resonance because the caps
> have low Q.
There is still one thing that I don´t fully understand about Rick's
method.
The resonance of the power plane capacitance with the capacitors
inductance depends on the number and package of the capacitors ( the
capacitors inductance is related to the package). I don´t see how
changing the capacitors value (capacitive) can modify the position or
peak of that resonce.
IMHO 20 0.1uF capacitors will have the same resonance with the power
plane as 20 0.001uF capacitors (or even 10 0.01uF plus 10 0.001uF)
So far I've been decoupling using different value capacitors because
that's the method that Xilinx recomends, but whithout seeing much logic
in the use of small value capacitors (if higher value can be used in
the same package). Now I think that Simon´s metod makes more sense.
Regards
rickman
Do you know the edge rate of your drivers on the SDRAM interface? They
are likley sub-nanosecond which means you need to consider both the SI
issues and the power distribution issues. It was not that long ago
that many PC motherboards could not work correctly with a third or
fourth SDRAM module plugged in because they did not do their homework
on SI issues. Now we are up to DDR2 speeds and are seeing the same
problems. But that does not mean you can ignore SDRAM SI issues. The
circuits are still the same and the edge rates can get you if you don't
give them their proper attention.
If you have a working board you can measure the ground/power bounce
rather easily. I think I described it before, but here it is again.
Write code to switch all the data bus and address bus signals in the
same direction at one time. Set some other output near these pins to a
constant level. Watch this constant output and see if you get a glitch
on this pin when the others change. This is the amplitude of the
bounce on your device. There may be additional noise on the
power/ground planes that comes from other chips so this may not be the
worst case noise the chip will see.
On a separate note, I can't believe some of the things we do here. Our
digital circuits are part of RF equipment so we are typically very
concerned with even low levels of noise in the RF region. To make sure
our boards are quiet we have an RF person review the design and board
layout. I was assisting on a design for a simple MCU board with an
attached GPS receiver. The RF guy was very concerned about various
noise sources that had burned him in the past and did a lot of what I
thought was overkill in the power distribution. I just found out that
he had the 6 layer stackup done with two ground planes and no power
plane! I suggested to the layout guy that it would be ok to flood fill
the signal layers with power plane and he said they are doing that, but
connecting to ground instead of power!!! So there is no effective
bypassing on this board above a couple hundred MHz and the freq of the
receiver is around 1.5 GHz. Do you think we will see any interference?
John_H
> "Symon" <symon_...@hotmail.com> writes:
>
>
>> I contend that the package impedance of modern FPGAs is such that any
>> benefit that a board wide power plane's capacitance could provide to your
>> design, over and above that which you can get from a small local plane and
>> associated bypass capacitors, is negligible. The caps work up to a few
>> hundred MHz, just about where the package stops working. Any noise on the
>> supply above this frequency doesn't get to the silicon anyway.
>
> I'll chip in one more point (which I have not data for, but discussion
> may be enlightening :-)..
>
> Even above the frequency at which the die won't see the noise due to
> the package inductance, the noise on the planes may still cause
> problems in passing EMC emissions tests, so you still have to be
> careful at the top end.
>
> Out of interest - do you consider how your mini-planes resonate at
> high frequencies?
>
> Cheers,
> Martin
The data I saw suggested that larger boards have plane resonance issues
at lower frequencies. The mini-plane approach would deliver less
overall capacitance compared to a full plane but the resonances would be
much higher in frequency since the transmission-line effects of the
"open" at the board edge have a much shorter quarter-wavelength for a
higher frequency before plane resonance.
rickman
The problem with trying to analyze this sort of design is that the
board does what it wants and does not care what you or I think it
should do. If you want to understand what is happening, you can read
Ritchey's book or you can do some simulations and measurements
yourself. Obviously others are not convinced, but what I learned in
this course and read in his book has me convinced about the utility of
the method.
I don't want to criticize anyone else's technique since I can't say for
sure what will work and what won't. But analyzing a design on paper
can give you a false sense of security until you simulate it or test
it. Rather than state an opinion, try it!
On the other hand, you should also consider that the SRF of the
different value caps is different. So why would they have the same
resonance when coupled to a plane?
rickman
> The data I saw suggested that larger boards have plane resonance issues
> at lower frequencies. The mini-plane approach would deliver less
> overall capacitance compared to a full plane but the resonances would be
> much higher in frequency since the transmission-line effects of the
> "open" at the board edge have a much shorter quarter-wavelength for a
> higher frequency before plane resonance.
Yes, if you eliminate the plane altogether you will not have any
resonances!!!
A resonance is not totally bad. It is only bad if the impedance is
above the level that you can tolerate. The goal is to maintain a low
impedance over a wide range of frequencies. If you make the plane
smaller you may push the resonance higher in frequency, but you also
increase the impedance across the high end of the band.
At edge rates of a nanosecond or less, the power plane capacitance is
the only capacitance that is effective to preserve the edge and to
reduce the resulting EMI. If you cut your planes into tiny regions
that have a fraction of the capacitance of the total board you will be
greatly increasing the impedance at these frequencies. There is no
other way to reduce this impedance.
The resonance peaks in impedance can easily be minimized by using low Q
capacitors. If you avoid C0G type parts and work with a range of
capacitance values you should not see a problem. If you use a tiny
power plane you will have a high impedance at the higher frequencies
and your signal edge rates and EMI will suffer.
The only down side to using multiple capacitor sizes is that you have
three line items on the BOM in place of one. On most of my BOMs I
already have at least two of these values anyway. I like to keep my
BOMs clean, but it seems silly to let this goal drive your decoupling
solution.
John_H
> Yes, if you eliminate the plane altogether you will not have any
> resonances!!!
You'll have no resonances but the inductance from the caps you have will put
a high upper limit on your impedance, agreed totally.
What is a problem is that the board when in a geometrical resonance - not an
LC issue but a transmission line issue where the open ends of the plane
reflect energy back around a quarter wavelgnth - the upper end of the
transmission-line resonance is an extremely high impedance. It's these
values that very high frequencies can't have plane-level decoupling benefit
them. Different areas of the board will experience different resonances and
even different resonant modes based on the geometry. These modes can be
predicted to help determine "better" places for caps that *can* still help
on large geometry boards.
> A resonance is not totally bad. It is only bad if the impedance is
> above the level that you can tolerate. The goal is to maintain a low
> impedance over a wide range of frequencies. If you make the plane
> smaller you may push the resonance higher in frequency, but you also
> increase the impedance across the high end of the band.
Absolutely. There's less distributed plane capacitance because there's less
plane. It's an issue of tradeoffs if your point of interest is a
geometry-driven resonance that can't easily be quashed with available caps.
> At edge rates of a nanosecond or less, the power plane capacitance is
> the only capacitance that is effective to preserve the edge and to
> reduce the resulting EMI. If you cut your planes into tiny regions
> that have a fraction of the capacitance of the total board you will be
> greatly increasing the impedance at these frequencies. There is no
> other way to reduce this impedance.
One way would be to use more esoteric ground/power distribution layers.
While the early distributed capacitance solutions beyond simple thin
dielectrics produced 2 mil FR4 layers between power and ground, there are
other materials available now (none of which I've had the joy to use) down
to 8 mil, some using higher dielectric constant materials to increase the
distributed capacitance further. The geometry can stay the same with better
capacitance or the geometry can be reduced without compromising the
distributed capacitance. It's a cost vs. perceived benefit issue here.
> The resonance peaks in impedance can easily be minimized by using low Q
> capacitors. If you avoid C0G type parts and work with a range of
> capacitance values you should not see a problem. If you use a tiny
> power plane you will have a high impedance at the higher frequencies
> and your signal edge rates and EMI will suffer.
The low-ESR C0G (NPO) style caps aren't necessarily a no-no, it's just that
the SRFs have to be closer (hence more cap values) in order to reduce the LC
resonance peaks between SRFs brought on by high-Q caps. It's probably best
to stick with low ESR but there may be some solutions where the higher SRFs
(I'm assuming they're better, not certain) may provide better coverage in a
specific high frequency range.
> The only down side to using multiple capacitor sizes is that you have
> three line items on the BOM in place of one. On most of my BOMs I
> already have at least two of these values anyway. I like to keep my
> BOMs clean, but it seems silly to let this goal drive your decoupling
> solution.
I would have thought more than 3 line items would be appropriate but the
information I saw might not have realized the benefits from low-Q caps.
I really like the possibilities with "good" bypassing design.
John_H
>
> On a separate note, I can't believe some of the things we do here. Our
> digital circuits are part of RF equipment so we are typically very
> concerned with even low levels of noise in the RF region. To make sure
> our boards are quiet we have an RF person review the design and board
> layout. I was assisting on a design for a simple MCU board with an
> attached GPS receiver. The RF guy was very concerned about various
> noise sources that had burned him in the past and did a lot of what I
> thought was overkill in the power distribution. I just found out that
> he had the 6 layer stackup done with two ground planes and no power
> plane! I suggested to the layout guy that it would be ok to flood fill
> the signal layers with power plane and he said they are doing that, but
> connecting to ground instead of power!!! So there is no effective
> bypassing on this board above a couple hundred MHz and the freq of the
> receiver is around 1.5 GHz. Do you think we will see any interference?
The situation might not be so bad. When an RF engineer is interested in
quiet power, there are filters between any noisy digital power planes and
the power for the RF section, effectively eliminating any bypass gains
achieved from the beautifully bypassed (but still RF-sensitivity
compromising) power planes.
There is a large variety of RF caps specifically used for in-line power
decoupling that are effective *only* at the high frequencies partly because
that's the only frequency of interest in the RF device. An oscillator at
1.5 GHz cares little about what's happening at 200 MHz if that 200 MHz noise
has been filtered out before hitting the effective 1.5 GHz bypassing.
The truely effective board level decoupling can result in much better
mixed-signal performance where discretes are connected directly to the
shared power plane. True RF still seems like a much different animal to me
where grounds really are king (with properly filtered and cascaded power
distribution is regal as well).
Symon
news:upsehj...@trw.com...
> "Symon" <symon_...@hotmail.com> writes:
>
>
> > I contend that the package impedance of modern FPGAs is such that any
> > benefit that a board wide power plane's capacitance could provide to
your
> > design, over and above that which you can get from a small local plane
and
> > associated bypass capacitors, is negligible. The caps work up to a few
> > hundred MHz, just about where the package stops working. Any noise on
the
> > supply above this frequency doesn't get to the silicon anyway.
>
> I'll chip in one more point (which I have not data for, but discussion
> may be enlightening :-)..
>
> Even above the frequency at which the die won't see the noise due to
> the package inductance, the noise on the planes may still cause
> problems in passing EMC emissions tests, so you still have to be
> careful at the top end.
>
> Out of interest - do you consider how your mini-planes resonate at
> high frequencies?
>
> Cheers,
> Martin
>
As John says in his post, both the capacitance and dimensions of the
'mini-plane' is much smaller than a big plane, so its capacitance and
quarter-wavelength is much smaller. This means that at the frequency at
which the bypass caps and plane would potentially resonate is where the
capacitors' ESR is huge. According to the Murata tool I linked in a previous
post, a 0402 X5R 1uF cap has an ESR of 1 ohm at 3GHz and rises with
frequency beyond that. This ESR damps any potential resonance. Another
reason why crappy Q is a good thing in this case.
Cheers, Syms.
Symon
> method.
> The resonance of the power plane capacitance with the capacitors
> inductance depends on the number and package of the capacitors ( the
> capacitors inductance is related to the package). I don“t see how
> changing the capacitors value (capacitive) can modify the position or
> peak of that resonce.
> IMHO 20 0.1uF capacitors will have the same resonance with the power
> plane as 20 0.001uF capacitors (or even 10 0.01uF plus 10 0.001uF)
>
> So far I've been decoupling using different value capacitors because
> that's the method that Xilinx recomends, but whithout seeing much logic
> in the use of small value capacitors (if higher value can be used in
> the same package). Now I think that Simon“s metod makes more sense.
>
> Regards
So, the resonance is between the sum of the capacitance of the plane and the
bypass cap and the inductance of the bypass cap. (The plane has very little
inductance to contribute.) Using different values changes the total
capacitance, I guess. The sims do show this effect, but they also show new
resonances between different valued caps, but these are generally smaller
than the plane resonance as the ESR of the bypass cap damps any resonance.
Cheers, Syms.
Symon
>
> On a separate note, I can't believe some of the things we do here. Our
> digital circuits are part of RF equipment so we are typically very
> concerned with even low levels of noise in the RF region. To make sure
> our boards are quiet we have an RF person review the design and board
> layout. I was assisting on a design for a simple MCU board with an
> attached GPS receiver. The RF guy was very concerned about various
> noise sources that had burned him in the past and did a lot of what I
> thought was overkill in the power distribution. I just found out that
> he had the 6 layer stackup done with two ground planes and no power
> plane! I suggested to the layout guy that it would be ok to flood fill
> the signal layers with power plane and he said they are doing that, but
> connecting to ground instead of power!!! So there is no effective
> bypassing on this board above a couple hundred MHz and the freq of the
> receiver is around 1.5 GHz. Do you think we will see any interference?
>
To me, it sounds as if your RF guy is doing exactly the right thing. It's
what I would do. I'm interested in what coupling paths you see which could
produce interference.
Anyway, I'll let you into a little secret! At my workplace a few years back,
an RF/Microwave guy started working. He's now moved on, but we remain good
friends. I've learnt so much stuff from this guy, indeed, enough to be
confident in posting and backing up my ideas and thoughts about bypass caps
and PDSs on a public forum.
So, why not buy your RF guy a few beers and listen to his thoughts on why he
did what he did? You might even like to print out bits of this thread and
ask his opinion. If nothing else, it'll be cheaper than taking a class. ;-)
Anyway, be sure to report back on what happens with the board.
Best regards, Syms.
rickman
> As John says in his post, both the capacitance and dimensions of the
> 'mini-plane' is much smaller than a big plane, so its capacitance and
> quarter-wavelength is much smaller. This means that at the frequency at
> which the bypass caps and plane would potentially resonate is where the
> capacitors' ESR is huge. According to the Murata tool I linked in a previous
> post, a 0402 X5R 1uF cap has an ESR of 1 ohm at 3GHz and rises with
> frequency beyond that. This ESR damps any potential resonance. Another
> reason why crappy Q is a good thing in this case.
If the tool says the SRF is 3 GHz, I can't argue with that. But I
don't believe it. The SRF for a 1 uF 0402 cap is typically below 10
MHz. Even many "low inductance" capacitors have a SRF of below 200
MHz. This is a very big discrepancy and will change your entire
perspective if it is wrong. I susgest you verify this number. Is it
possible that the SRF is 3 MHz?
With a SRF below 10 MHz, it does not matter a lot where the parallel
resonance is. There will be a wide range of frequencies between the
SRF and where the plane has a low impedance that will have a very high
impedance irrrespective of any resonance.
Another thing, "high" ESR is good, but not so high that it interferes
with the function of the capacitor. With a 1 ohm ESR it will not be a
very good capacitor at lower frequencies where it is supposed to be
capacitive.
rickman
> "rickman" <gnu...@gmail.com> wrote in message
> news:1157032693.2...@h48g2000cwc.googlegroups.com...
> >
> > On a separate note, I can't believe some of the things we do here. Our
> > digital circuits are part of RF equipment so we are typically very
> > concerned with even low levels of noise in the RF region. To make sure
> > our boards are quiet we have an RF person review the design and board
> > layout. I was assisting on a design for a simple MCU board with an
> > attached GPS receiver. The RF guy was very concerned about various
> > noise sources that had burned him in the past and did a lot of what I
> > thought was overkill in the power distribution. I just found out that
> > he had the 6 layer stackup done with two ground planes and no power
> > plane! I suggested to the layout guy that it would be ok to flood fill
> > the signal layers with power plane and he said they are doing that, but
> > connecting to ground instead of power!!! So there is no effective
> > bypassing on this board above a couple hundred MHz and the freq of the
> > receiver is around 1.5 GHz. Do you think we will see any interference?
>
> The situation might not be so bad. When an RF engineer is interested in
> quiet power, there are filters between any noisy digital power planes and
> the power for the RF section, effectively eliminating any bypass gains
> achieved from the beautifully bypassed (but still RF-sensitivity
> compromising) power planes.
Yes, he added an LDO between the switcher and the digital power because
the digital power goes to the GPS module. This is a bit pointless
because an LDO is only effective up to a few 10s of kHz. Then there is
a ferrite bead which is not very effective until you get to high MHz.
So that leaves a huge hole from about 100 kHz to maybe 100 MHz. Also
the ferrite bead is only an impedance, not a cure. Noise can still
couple to the load if it is not a low impedance.
On the other hand a good power plane will decouple noise at the source
and prevent it from reaching the ferrite filter. So good power planes
are *always* a good thing for reducing noise.
> There is a large variety of RF caps specifically used for in-line power
> decoupling that are effective *only* at the high frequencies partly because
> that's the only frequency of interest in the RF device. An oscillator at
> 1.5 GHz cares little about what's happening at 200 MHz if that 200 MHz noise
> has been filtered out before hitting the effective 1.5 GHz bypassing.
How do you make a capacitor less effective at low frequencies???
Wouldn't that be an inductor?
> The truely effective board level decoupling can result in much better
> mixed-signal performance where discretes are connected directly to the
> shared power plane. True RF still seems like a much different animal to me
> where grounds really are king (with properly filtered and cascaded power
> distribution is regal as well).
I don't know about the royal lineage. I do know that digital circuits
are kept quiet with good power decoupling including low impedance
across the spectrum. In this case the only way to filter 1.5 GHz in
the power spectrum is with plane to plane capacitance.
rickman
> Rick,
> To me, it sounds as if your RF guy is doing exactly the right thing. It's
> what I would do. I'm interested in what coupling paths you see which could
> produce interference.
I think you should talk to the RF guy about that. He is responding to
problems he had in the past that were fixed without understanding the
cause. So now he is using the same bandaid to a problem that does not
exist. BTW, the LDO he used in another design was to fix a noise
problem in an audio circuit that obviously was due to lack of good
power supply design.
I see the main path for noise being the power distribution. If you
keep that clean the only other path is coupling by emitted signals
which are also reduced by good power decoupling.
> Anyway, I'll let you into a little secret! At my workplace a few years back,
> an RF/Microwave guy started working. He's now moved on, but we remain good
> friends. I've learnt so much stuff from this guy, indeed, enough to be
> confident in posting and backing up my ideas and thoughts about bypass caps
> and PDSs on a public forum.
>
> So, why not buy your RF guy a few beers and listen to his thoughts on why he
> did what he did? You might even like to print out bits of this thread and
> ask his opinion. If nothing else, it'll be cheaper than taking a class. ;-)
I had a conversation with him where I learned that his LDO in the
digital power was a response to touching a hot stove. I don't have a
lot of respect for that type of engineering. I also don't respect
engineering that does not address problems with understanding. Rather
than learn why the switching supply was making a low frequency noise he
now adds LDOs to the power path for all digital circuits. That would
not be so bad, but this is battery operated equipment and this has
increased our power budget by over 13%.
Anytime someone can show me a problem and tell me how an approach will
solve the problem I am happy to listen. But adding circuits when there
is no problem is not a good idea.
> Anyway, be sure to report back on what happens with the board.
I don't consider that to be the discriminator of what approach is
correct. The digital circuitry is very small and likely not to create
any major problems. But it is also likely to cause a small decrease in
sensitivity that might be hard to measure without doing a performance
test. I know they will not be doing any performance testing on this
receiver. They will just fire it up and see if it can find the
satellites in the factory. So no one will be right and no one will be
wrong.... until the customer compares our units to a comercial GPS
receiver and we don't hold track as well. But then it will be far too
late to make changes. It would be much better to do it right the first
time.
Symon
that small planes do not have a bypass resonance problem.
1) With a tiny plane, the resonance between it and the bypass caps is at a
very high frequency.
2) At this frequency, the bypass caps have a high ESR.
3) This damps the resonance so much that you don't have a any problem at
all.
At no point did I say that a 1uF cap had a SRF of 3GHz. (BTW, you're quite
correct that it's at about 10MHz) I did mention its ESR at 3GHz to give an
example of how the ESR increases with frequency. The frequency we are
talking about is the resonant frequency between the plane and the bypass
caps.
HTH, Syms.
John_H
> John_H wrote:
>> "rickman" <gnu...@gmail.com> wrote in message
>> news:1157032693.2...@h48g2000cwc.googlegroups.com...
<snip>
>> There is a large variety of RF caps specifically used for in-line power
>> decoupling that are effective *only* at the high frequencies partly
>> because
>> that's the only frequency of interest in the RF device. An oscillator at
>> 1.5 GHz cares little about what's happening at 200 MHz if that 200 MHz
>> noise
>> has been filtered out before hitting the effective 1.5 GHz bypassing.
>
> How do you make a capacitor less effective at low frequencies???
> Wouldn't that be an inductor?
All capacitors are less effective at lower frequencies. They don't do much
to your kHz signals whereas an inductor can be a dead short at the lower
frequencies. It's just that if you use a 10 pf RF capacitor with
appropriate multi-GHz leads for stripline design, you won't do a whole lot
at 100 MHz but where the circuit is used - the GHz realm - this low-value
capacitor can provide excellent RF bypass.
>> The truely effective board level decoupling can result in much better
>> mixed-signal performance where discretes are connected directly to the
>> shared power plane. True RF still seems like a much different animal to
>> me
>> where grounds really are king (with properly filtered and cascaded power
>> distribution is regal as well).
>
> I don't know about the royal lineage. I do know that digital circuits
> are kept quiet with good power decoupling including low impedance
> across the spectrum. In this case the only way to filter 1.5 GHz in
> the power spectrum is with plane to plane capacitance.
Digital circuits are clocked, extremely wideband devices. RF is typically
narrowband. Also, the power supplies are typically filtered in stages on
the receive side such that the highest level output (IF amplifier out,
perhaps) is closest to the "main" rails while the next stage down is
filtered from that filtered rail. This goes down until you're at the Low
Nois Amplifier attaches to the antenna where the power has passed through
several filter stages. If everything was connected to one power/ground
sandwich, the circuit would be losing its lunch. No sensitivity at all.
About the only way to filter 1.5 GHz for a digital circuit - extremely
wideband by nature - is with distributed plane capacitance.
I still suggest that RF is a different beast where power planes are no help.
fpga...@yahoo.com
rickman wrote:
> I don't want to criticize anyone else's technique since I can't say for
> sure what will work and what won't. But analyzing a design on paper
> can give you a false sense of security until you simulate it or test
> it. Rather than state an opinion, try it!
This discussion has gotten so interesting, I think try it is the only
thing left.
I'd front the few hundred dollars, and some layout time, to take 2-3
designs and lay them out with the Xilinx guidelines, Rick's guidelines,
and Symon's Guidelines and do a bake off if somebody would provide the
parts. Say 3 pieces of a 6 layer 0.063 FR4 panel that is 16" x 22",
would allow for 2 projects that are 7" x 8", or 3 projects that are 5"
X 7".
Should be fun :)
John_H
news:44f72...@x-privat.org...
> I think you've missed the point I'm trying to make. I'm trying to point
> out
> that small planes do not have a bypass resonance problem.
> 1) With a tiny plane, the resonance between it and the bypass caps is at a
> very high frequency.
> 2) At this frequency, the bypass caps have a high ESR.
> 3) This damps the resonance so much that you don't have a any problem at
> all.
>
> At no point did I say that a 1uF cap had a SRF of 3GHz. (BTW, you're quite
> correct that it's at about 10MHz) I did mention its ESR at 3GHz to give an
> example of how the ESR increases with frequency. The frequency we are
> talking about is the resonant frequency between the plane and the bypass
> caps.
>
> HTH, Syms.
You mentioned an ESR at 3 GHz. ESR is important near SRF and at resonance
points, not much use elsewhere.
as for your points
1) your cap/board resonance problems are just moved with smaller planes, not
removed. Another problem is resonance either between caps with SRFs far
enough apart (given the associated Qs) or caps that are inductively far
apart, forcing the different SRFs to the perspective of a specific noise
source.
2) an ESR of 1 ohm isn't so bad if you have a dozen caps "nearby" but 83
mOhms still isn't that great for high power problems
3) Ah, life with no problems. Resonance between the cap and plane might not
be such a problem if the Q drops as the frequency increases, but what
impedance solution are you achieving? If you need more high-SRF caps to
bring down the impedance beyond the SRF, the effective ESR of the "solution"
is lower and resonance is still a consideration. Isn't it?
I'd suggest that most of the folks in this forum don't need the 3GHz
performance because the packaged digital logic is loally bypassed in the
package and the silicon so they don't "feel" much above many 10s of MHz, at
least according to the recent Howard Johnson talk. It's the other discretes
on board - the unpackaged or "low package" devices that feel the brunt of
the plane problems.
...and EMI.
Symon
I interspersed some comments.
"John_H" <news...@johnhandwork.com> wrote in message
news:h8HJg.175$za1...@news02.roc.ny...
>
> You mentioned an ESR at 3 GHz. ESR is important near SRF and at resonance
> points, not much use elsewhere.
>
resonance, e.g. between bypass caps and plane. That's what I'm addressing
here.
>
> as for your points
> 1) your cap/board resonance problems are just moved with smaller planes,
not
> removed.
>
resonant parts, in this case the bypass cap, has a large ESR, the resonance
can't happen as it's damped away.
>
> Another problem is resonance either between caps with SRFs far
> enough apart (given the associated Qs) or caps that are inductively far
> apart, forcing the different SRFs to the perspective of a specific noise
> source.
>
> 2) an ESR of 1 ohm isn't so bad if you have a dozen caps "nearby" but 83
> mOhms still isn't that great for high power problems
>
decoupling at frequencies above a few hundred MHz is useless because of the
package impedance at these frequencies.
>
> 3) Ah, life with no problems. Resonance between the cap and plane might
not
> be such a problem if the Q drops as the frequency increases, but what
> impedance solution are you achieving? If you need more high-SRF caps to
> bring down the impedance beyond the SRF, the effective ESR of the
"solution"
> is lower and resonance is still a consideration. Isn't it?
>
MHz. This 'threadlet' starting with Martin's post is addressing mini-plane
resonance issues, not bypassing. I wish I'd never mentioned 3 bloody GHz
now! :-)
>
> I'd suggest that most of the folks in this forum don't need the 3GHz
> performance because the packaged digital logic is loally bypassed in the
> package and the silicon so they don't "feel" much above many 10s of MHz,
at
> least according to the recent Howard Johnson talk. It's the other
discretes
> on board - the unpackaged or "low package" devices that feel the brunt of
> the plane problems.
>
> ...and EMI.
>
>
Cheers, Syms.
fpga...@yahoo.com
Symon wrote:
> I'm not suggesting that decoupling at 3GHz is useful. In my opinion, any
> decoupling at frequencies above a few hundred MHz is useless because of the
> package impedance at these frequencies.
Which is a real design issues as we have FPGA's which have the ability
to clock internally above a few hundred MHz, and the VCCINT pins have
strong frequency components spaced at multiples of the LUT propagation
delay, and the short inter-CLB interconnects. And, with each
generation, they move higher up the scale.
> To repeat myself, I don't care what the impedance is above a few hundred
> MHz. This 'threadlet' starting with Martin's post is addressing mini-plane
> resonance issues, not bypassing. I wish I'd never mentioned 3 bloody GHz
> now! :-)
All the issues are related, particularly since Austin started this
thread in response to my posting that I stacked caps as a secondary
check that there was enough bulk capacitance in proto layout, in a case
where I thought that the chip/package was unable to handle worst case
designs.
rickman
> I think you've missed the point I'm trying to make. I'm trying to point out
> that small planes do not have a bypass resonance problem.
> 1) With a tiny plane, the resonance between it and the bypass caps is at a
> very high frequency.
> 2) At this frequency, the bypass caps have a high ESR.
> 3) This damps the resonance so much that you don't have a any problem at
> all.
>
> At no point did I say that a 1uF cap had a SRF of 3GHz. (BTW, you're quite
> correct that it's at about 10MHz) I did mention its ESR at 3GHz to give an
> example of how the ESR increases with frequency. The frequency we are
> talking about is the resonant frequency between the plane and the bypass
> caps.
I misunderstood. It is getting a bit pointless to continue to discuss
this as the only thing that is important is how it works. We can get
info on how we expect it to work by doing simulations and analysis, but
measurement is the only way to be sure. But I don't think we even
agree on what constitutes the requirement in terms of impedance.
A tiny plane will have nearly no capacitance. The resulting resonance
is not important since the plane will not be doing much good as a
capacitor.
I don't understand what problem is being solved by using a small power
plane. A large power plane is useful when used with a combination of
values of caps with low Q values. This arrangement can work well with
three values of ceramic caps and one value of tantalum cap and give a
relatively flat, low impedance from 1 kHz to well above a GHz. But if
you cut up your power plane so that it is very small, the upper end
will be limited to a few hundered MHz which is not fast enough for many
applications with fast edge rates.
Using a single value of ceramic cap will never provide a low impedance
above 100-200 MHz and without a sizable plane will result in a high
impedance that will cause edge rates to slow and potentially induce
excessive bounce lowering your noise margin. With a full power plane
closely coupled to the ground plane you are likely to have a resonance
causing a high peak in the impedance around 100-200 MHz. Sure you can
use 4 or 5 times the number of caps to lower this peak, but why do that
when you can do it more easily with fewer caps?
rickman
> I'd suggest that most of the folks in this forum don't need the 3GHz
> performance because the packaged digital logic is loally bypassed in the
> package and the silicon so they don't "feel" much above many 10s of MHz, at
> least according to the recent Howard Johnson talk. It's the other discretes
> on board - the unpackaged or "low package" devices that feel the brunt of
> the plane problems.
I am not aware of the HJ talk on packages limiting the need for high
frequency decoupling. But I seriously doubt that this is an accurate
statement if it was made. If a chip can produce a rise time of 0.5 nS
then clearly the power plane is providing enough current at very high
frequencies to drive the transmission line. I don't see how the chip
could possibly provide enough coulombs to drive the line without the
power coming from the power plane.
Is it possible that HJ was referring to the packages with higher lead
inductance (any type of leaded package such as SSOP, TSSOP or QFP)
compared to BGA and CSP?
rickman
> Digital circuits are clocked, extremely wideband devices. RF is typically
> narrowband. Also, the power supplies are typically filtered in stages on
> the receive side such that the highest level output (IF amplifier out,
> perhaps) is closest to the "main" rails while the next stage down is
> filtered from that filtered rail. This goes down until you're at the Low
> Nois Amplifier attaches to the antenna where the power has passed through
> several filter stages. If everything was connected to one power/ground
> sandwich, the circuit would be losing its lunch. No sensitivity at all.
This is a GPS module. The you are talking about the power normally
delivered to the analog portion of a receiver design. This filtering
was put on the digital section of the GPS module. The LDO accomplished
*nothing* since there was no reason to suspect noise in the bandwidth
the LDO could filter. Since the digital section would make its own
noise, I see no point to adding an inductor to the path from the
switcher to the digital LDO. The only inductor he put in the path to
the RF was the ferrite which was only effective in the hunderds of MHz.
There are lots of frequencies in the noise that can easily get into
the RF section and mess things up. Noise does not have to be on the
carrier frequency.
This is a poor design and leaving off a power plane just compounds the
problem.
> About the only way to filter 1.5 GHz for a digital circuit - extremely
> wideband by nature - is with distributed plane capacitance.
>
> I still suggest that RF is a different beast where power planes are no help.
Isn't 1.5 GHz RF? If the noise is present on the power rail at this
frequency it will be radiated by every part that is connected. This
will be picked up by any other circuitry in the area and possibly even
the antenna.
So instead of providing power planes to prevent the high freq current
from creating EMI, they are adding cans around the various circuits.
The GPS module already has a can on it. Our digital design has not
one, but three to isolate each section of the circuit!!!
I am totally convinced that this guy is winging it and has no concept
of how to deal with EMI. Basically he has been working at this place
for the last 10 years (where cost is often not an issue) and has not
learned much about how to best deal with EMI. Instead he has learned a
handful of "tricks" that work as long as you don't care about how much
your solution costs and you don't mind tweeking the design after it is
built.
Symon
> Symon wrote:
>
> It is getting a bit pointless to continue to discuss
> this as the only thing that is important is how it works. We can get
> info on how we expect it to work by doing simulations and analysis, but
> measurement is the only way to be sure. But I don't think we even
> agree on what constitutes the requirement in terms of impedance.
>
I totally agree. Both your designs and mine work, and we've had a robust but
civil and highly enjoyable discussion of the issues. I've certainly learned
some things from this conversation, thanks for your time and thoughts!
I still disagree with the other points in your post, but I've already
detailed why in my previous posts, so I'll just have to live with that.
Thanks again, and best regards, Syms.
John_H
<snip>
> If a chip can produce a rise time of 0.5 nS
> then clearly the power plane is providing enough current at very high
> frequencies to drive the transmission line. I don't see how the chip
> could possibly provide enough coulombs to drive the line without the
> power coming from the power plane.
>
> Is it possible that HJ was referring to the packages with higher lead
> inductance (any type of leaded package such as SSOP, TSSOP or QFP)
> compared to BGA and CSP?
It was a BGA package with on-package decoupling and - for highest
frequencies - capacitance in the silicon.
If you ask yourself how many coulombs are associated with a single
switching event and compare it to the energy stored in an 0402 capacitor
you might be surprised. These things look nearly like AC shorts at
their SRFs, after all.
John Larkin
>Austin Lesea wrote:
>> To the subject at hand: placing additional caps across existing caps
>> does not reduce the noise (unless the dominant cause is lack of adequate
>> capacitance).
>>
>> The reason why the noise is bad is that the L (as in Ldi/dt) is most
>> likely the largest, and most dominant factor, in the form of the via and
>> traces to the bypass capacitor.
>>
>> Many times people have placed additional caps on top of the the existing
>> caps and wondered why the noise is not reduced: well, you did not
>> change the L in the equation, did you. So why did you expect V to change?
>>
>> You may have moved the resonant frequency (more often not), but often
>> people make the mistake of assuming that a 0.1uF requires a 0.01uF and a
>> 0.001uF in parallel. You can see that if the series L is dominant, you
>> haven't even moved the frequency by more than a few percent by the small
>> amount of additional capacitance.
>
>What do you think about the idea that if the caps are connected
>directly to good low impedance power planes that the location of the
>caps are not critical at all. I have been discussing this in
>comp.arch.embedded and have not gotten much negative feedback except
>some claim that more is always better and that multiple values are not
>needed.
>
I sometimes add a few SMA connector footprints to multilayer boards so
I can TDR the planes. As near as I can measure with my Tek 20 GHz TDR,
on a bare VME-sized (6U) board, good parallel planes look like an
ideal capacitor, with no evidence of edge reflections or anything like
that. And as you load ceramic bypass caps *anywhere* on the board, the
value of the ideal cap increases. So it doesn't much matter where you
put bypass caps.
The planes are a better cap than any discrete parts. Keep the
powerplane to ground dielectric thin, 5 mils or less, to keep the
plane capacitance high.
John
John Larkin
>John_H wrote:
>> "rickman" <gnu...@gmail.com> wrote in message
>> Won't any higher inductance result in the same above-SRF slope? That is,
>> given the total inductance, it won't matter what the capacitance is once
>> above an ohm in the impedance vs freq plot.
>
>I'm not sure what you are asking. A different capacitance will not
>change the inductive part of the impedance curve and a different
>inductance will not change the capacitive part of the curve. What
>changes in both cases is the SRF. So you put a few 0.1 uF caps on the
>board and a number more of 0.01 uF caps and even more of the 0.001 uF
>caps. Each capacitance value needs to have sufficient quantity to
>bring the impedance near the SRF low enough to be effective. Then the
>capacitive effect of the smaller caps keep the overall impedance low in
>spite of the larger caps being inductive.
There's nothing wrong with a cap being inductive as long as the
inductance is low. If somebody made a 10 farad 0603 cap, its SRF might
be a kilohertz or something, but having more C, and operating above
srf, doesn't make it any worse a high-frequency bypass. I figure the
more C, the better for any given size.
PCB planes are a big, lossy, many-nF capacitors (or, if you prefer,
big, lossy, super-low Z transmission lines), and adding lots of, say,
0.33 uF 0603 caps just makes it better. All this stuff about Spicing
staggered srf nulls is silly, given that the caps aren't out in space,
they're soldered to the huge low-z lossy power planes.
John
John_H
Have you verified that you can use a 50 ohm TDR to effectively measure
impedance around 1 ohm and less?
Measurements have been made by others that suggest your readings aren't
telling you the whole story. It's possible the others are wrong and
you're correct but it seems there are several sources suggesting that a
6U board will NOT look like an ideal capacitor without inductive or
transmission line effects.
Martin Thompson
> I'm not suggesting that decoupling at 3GHz is useful. In my opinion, any
> decoupling at frequencies above a few hundred MHz is useless because of the
> package impedance at these frequencies.
and
> To repeat myself, I don't care what the impedance is above a few hundred
> MHz. This 'threadlet' starting with Martin's post is addressing mini-plane
> resonance issues, not bypassing. I wish I'd never mentioned 3 bloody GHz
> now! :-)
As I understand it, the reason you don't care above a few hundred MHz
is because you are doing mini-planes? If you were doing whole board
planes, then there may be problems above the "package frequency" due
to the PCB radiating at a frequency which is not "well-decoupled" even
at several hundred MHz. With a bigger plane, this is more likely.
Or have I misunderstood?
Cheers,
Martin
--
martin.j...@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
rickman
> There's nothing wrong with a cap being inductive as long as the
> inductance is low. If somebody made a 10 farad 0603 cap, its SRF might
> be a kilohertz or something, but having more C, and operating above
> srf, doesn't make it any worse a high-frequency bypass. I figure the
> more C, the better for any given size.
Another country heard from!
John, no one is saying more C is not better than less C. The question
is how do you provide *enough* C to do the job in the most cost
effective manner and be sure you have done the job right?
My point about the caps being inductive is that where a cap is near its
SRF, the impedance is much lower than either the capacitive curve or
the inductive curve. If you draw the impedance line for the equivalent
inductance and for the pure capacitance, they approximate the true
impedance of the part anywhere that is not near the SRF. So when I
talk about the region where the cap is inductive, I am talking about
the impedance rising to a point that it is no longer low impedance.
> PCB planes are a big, lossy, many-nF capacitors (or, if you prefer,
> big, lossy, super-low Z transmission lines), and adding lots of, say,
> 0.33 uF 0603 caps just makes it better. All this stuff about Spicing
> staggered srf nulls is silly, given that the caps aren't out in space,
> they're soldered to the huge low-z lossy power planes.
Well, I didn't know that "silly" was a technical evaluation. I guess
if you are designing a board for Jerry Lewis you should calculate the
SF (Silly Factor) as part of your evaluation. I think you are proving
my point. The caps are on a plane that will resonate with the caps.
So you can't just say adding caps will lower the impedance across the
bandwidth.
In fact, however, adding a single value of capacitor to a power plane
is likely to produce a parallel resonance (with a higher impedance than
the plane by itself) at a frequency that you care about. This can be
mitigated by the ESR of the caps which will damp the parallel
resonance. The data I saw showed that using 0603 caps of 0.1 uF will
produce a pretty healthy impedance peak in the 50-100 MHz range, of
course depending on the details of your board. This is a bad place to
have an impedance rise when you are looking for the caps to lower the
impedance.
A lot of people here seem to think that you can analyze this on paper
or with words. I have seen the simulation results and the measurement
results of real boards, so I am inclinded to believe that over any
paper analysis which may or may not be correct for a real board.
Sure, you might be able to make your board work with a hundred 0603
parts. But wouldn't it save money by reducing the routing congestion
on your board if you could reduce that to maybe 20 parts of three
different values? It certainly would save time in layout and may even
save you a pair of layers in a close board.
John Larkin
Except that, when you measure it, they do.
>
>In fact, however, adding a single value of capacitor to a power plane
>is likely to produce a parallel resonance (with a higher impedance than
>the plane by itself) at a frequency that you care about. This can be
>mitigated by the ESR of the caps which will damp the parallel
>resonance. The data I saw showed that using 0603 caps of 0.1 uF will
>produce a pretty healthy impedance peak in the 50-100 MHz range, of
>course depending on the details of your board. This is a bad place to
>have an impedance rise when you are looking for the caps to lower the
>impedance.
A scattering of 0.1 or 0.33 uf ceramic caps here and there about a
power plane will not induce meaningful resonances, as far as I can
measure. The only mistake I have ever made on multilayer boards was
using too many bypass caps. Lately I use four 0.33 uf caps per supply
per FPGA, and even that's probably overkill.
>
>A lot of people here seem to think that you can analyze this on paper
>or with words. I have seen the simulation results and the measurement
>results of real boards, so I am inclinded to believe that over any
>paper analysis which may or may not be correct for a real board.
I have seen a number of simulations that were absurd, generally -
surprise! - performed by guys who sell caps. What I believe are TDR
measurents on unpowered boards and plane noise measurements on
operating products.
>
>Sure, you might be able to make your board work with a hundred 0603
>parts. But wouldn't it save money by reducing the routing congestion
>on your board if you could reduce that to maybe 20 parts of three
>different values? It certainly would save time in layout and may even
>save you a pair of layers in a close board.
All of my boards work as described. The reason there are so many
opinions about bypassing is that most everybody's approach works. I
know one guy who doesn't use bypass caps at all, and his boards work
too.
John
fpga...@yahoo.com
John Larkin wrote:
> All of my boards work as described. The reason there are so many
> opinions about bypassing is that most everybody's approach works. I
> know one guy who doesn't use bypass caps at all, and his boards work
> too.
No caps at all on fpga boards :)
Now I know we need a bake off!!!
rickman
> On 1 Sep 2006 05:10:53 -0700, "rickman" <gnu...@gmail.com> wrote:
> >So you can't just say adding caps will lower the impedance across the
> >bandwidth.
>
> Except that, when you measure it, they do.
I don't know how you measured this. The measurement data I have seen
clearly shows this resonance. But it was not my data, it was from
someone much more knowledgeable than myself.
> All of my boards work as described. The reason there are so many
> opinions about bypassing is that most everybody's approach works. I
> know one guy who doesn't use bypass caps at all, and his boards work
> too.
I don't doubt that there are many ways to skin a cat. But I have seen
for myself boards that did not work well because of power decoupling
problems. The biggest symptom from poor power distribution is general
flakeyness. Often this is misdiagnosed as an SI issue, which I guess
is not totally wrong. But now I realize that the proper cause of poor
edge rates and some portion of bounce problems is in the power
distribution.
With no caps I would expect you have to be designing board with very
limited IO and low current devices. I seriously doubt that his method
would work on every product. The real point that was made in the class
I took was that you need to evaluate your power decoupling needs rather
than just applying a "rule of thumb". I guess some people do their
evaluation by saying, "I don't need no stinkin' caps".
;^)
John Larkin
wrote:
The complementary measurement is to use the same SMA tap to measure
plane noise on the operating board, which is a good way to verify
theory. I do boards that mix FPGA's, Eclips, uPs, fiber optics, PLLs,
VME interfaces, and precision delay generators, and they all work at
picosecond jitter levels. So far, close planes and reasonably
scattered 0.1 or 0.33 uF 0603 bypasses have always worked.
John
Symon
news:u1wqv2...@trw.com...
> "Symon" <symon_...@hotmail.com> writes:
>
>
> > I'm not suggesting that decoupling at 3GHz is useful. In my opinion, any
> > decoupling at frequencies above a few hundred MHz is useless because of
the
> > package impedance at these frequencies.
> and
>
> > To repeat myself, I don't care what the impedance is above a few hundred
> > MHz. This 'threadlet' starting with Martin's post is addressing
mini-plane
> > resonance issues, not bypassing. I wish I'd never mentioned 3 bloody GHz
> > now! :-)
>
> As I understand it, the reason you don't care above a few hundred MHz
> is because you are doing mini-planes? If you were doing whole board
> planes, then there may be problems above the "package frequency" due
> to the PCB radiating at a frequency which is not "well-decoupled" even
> at several hundred MHz. With a bigger plane, this is more likely.
>
> Or have I misunderstood?
>
> Cheers,
> Martin
>
Right. That's my reasoning.
Cheers, Syms.