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Message from discussion External Cloking of Altera MAX 7000S
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Mike  
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 More options Oct 8 1999, 3:00 am
Newsgroups: comp.arch.fpga
From: "Mike" <mmatu...@ics-ltd.com>
Date: 1999/10/08
Subject: Re: External Cloking of Altera MAX 7000S

Moussa Ba wrote in message <37FD1D45.848CC...@eng.umd.edu>...
>Thank you for your reply.  I forgot to mention in my email that I did use a
TTL
>crystal oscillator.  And I still get a messed up signal as soon as I
connect the

>clock to the clock input of the MAX chip.

Is it possible that you connect your clock to a wrong pin? Check how your
pins were routed in your .rpt file. It sounds like you are connecting your
clock to a pin configured as an output.

Mikhail Matusov


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