spartan 3 on 4 layers
colin
I have just finished routing a simple board with a 208 pin qfp spartan
3. I have just used top and bottom layers and it is time to add the
power. I need 3.3v for all IO and the 1.2v and 2.5v for vccint and
vccaux. I have not routed any signal under the spartan on either layer
so I plan to use GND on 1 inner layer and 3.3 on the fourth layer with
an island of 1.2 or 2.5 under the spartan with 2.5 or 1.2 then on the
bottom layer.
Just wondering if anyone can see any holes in this idea.
thanks
colin
Austin Lesea
Our SSO rules assume you have dedicated planes for Vccint, Vcco. If you
do not have both a power and a ground plane for each of these supplies,
the SSO numbers must be reduced. This also goes for simultaneously
switching CLBs, and not just IOs. We assume a power and ground plane
(yes that would be four layers just for power) for low inductance on the
Vccint/Vcco.
You might want to investigate the Point of Load concept (POL or POLA)
from TI (US) and Belkin (Japan).
By placing power supplies directly at the load, the loop inductance is
greatly reduced.
I have a SDRAM+2VP20 PCI pcb that has four layers, and operates very
well. Perhaps you pay more for a more capable power supply, but you pay
less for the PCB.
Remember that V=-LdI/dt. There is no way to reduce ground and Vcc
bounce without reducing either the I (current switched by reducing the
number of things switching), or reducing the L (indutance). The time
(dt) is not something that can be changed (as in internal nodes switch
time is fixed by process and design).
No amount of bypass caps will fix a bad pcb.
Austin
Symon
It's hard to answer this question without knowing what the FPGA is doing. If
the I/Os are switching slowly, but the logic inside is going very fast, then
your Vccint supply is of paramount importance. For example, if all the slew
rates in the IOBs are set to slow, the 3.3V rail maybe doesn't need to be on
a plane. In fact a crappy Vcco can sometimes actually help EMI problems by
slowing the IO signals. I'd say that as you're using a PQ208, high speed
stuff isn't foremost in your mind.
When Xilinx say that 'all the supplies are recommended to be on a plane',
what I guess they mean is 'we tried it with all the supplies on a plane and
it met ALL our specs'. They're not saying other methodologies won't work,
especially if you're not trying to meet the fastest switching rates.
Although wire-wrap's probably a bad idea!
What you can do is what I think you're suggesting, have mini-planes for each
supply, sharing the PCB layer. If you can also get some 0402 caps on the
top-side (fpga-side) of the board very close to the pins, that'll help a
lot. With the package you're using just go for the biggest value X5R cap you
can get, 1uF probably, and route it on the top layer straight to the pins.
This takes the via inductance out of the equation. Don't worry about all
that 'use several different values to widen the resonance', that's probably
mumbo-jumbo in the real world, especially with a PQ208. There are too many
parasitics around to confuse the issue. Small package (=low inductance), big
capacitance is what you want!
The point-of-load supplies Austin mentions are a good idea, but don't bust a
gut getting them close to the FPGA, just make sure the supply rails have
very low AC impedance near the FPGA. So, lots of point-of-load decoupling
and lots of copper is what you need!
If I were you, I'd be optimistic. You're thinking about this, which gives
you a much, much higher chance of success than some folks...
Good luck, Syms.
p.s. More reading:-
http://www.sigcon.com/pubsIndex.htm
Look at 'Bypass Capacitors'.
"colin" <colin_...@yahoo.com> wrote in message
news:885a4a4a.04101...@posting.google.com...
rickman
>
> "Tom Seim" <soar2...@yahoo.com> wrote in message
> news:6c71b322.04101...@posting.google.com...
> > Austin Lesea <aus...@xilinx.com> wrote in message
> >> No amount of bypass caps will fix a bad pcb.
> >
> > the high frequency current-they get recharged by power supply.
> > Granted, you need low impedance to recharge the caps before they are
> > used again, but the power supply is not supplying the fast edge
> > currents.
> ..but if your PCB puts too much inductance between the caps and the FPGA,
> this 'bad' PCB won't be fixed by merely adding more badly routed and
> positioned bypassing.
I think he was addressing the comments about keeping the PSU near the
chips. I have *never* heard anyone recommend that PSU placement would
affect the need for good PCB design. The range of frequencies that PSU
selection or placement would affect is way below the range of freqencies
that would be affected by PCB layout. I don't think anyone here is
talking about putting ceramic decoupling caps an inch from the chip
pins.
--
Rick "rickman" Collins
rick.c...@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
rickman
> > Tom,
> >
> > There is no "C" in Ldi/dt.
> >
> > If you can find out how varying a capacitance in any way changes the
> > induced bounce (V=-Ldi/dt), let me know.
> >
> > Bypass capacitance prevents rail collapse, but it does nothing to
> > prevent ground bounce (it can actually make it worse, as there is more
> > energy stored which makes di larger and dt faster).
> >
> > Austin
> [snip]
>
> I think the point being made here is that bypass caps located where the
> inductance between the caps and the chip is small, the i in di/dt *is*
> significantly altered if the i being discussed is power/ground plane
> inductance.
The L di/dt issue is a red herring. Every good engineer knows that *NO*
circuit is pure L or pure C or even pure R. All circuits are a
combination of the three (hopefully linear) and what matters is the
resulting Z.
> The regulator at the load should only help out if 1) the regulator has
> extremely fast response or 2) the current demands fluctuate at very high
> aplitudes at much lower frequencies.
NO regulator has enough speed to respond at the frequencies that power
planes address. Even if they did, the required distance between the
regulator and the chip would add L (increasing the Z) to a point that
counters the feature.
> When the bypass caps do their job in the frequency range they're designed
> for, the lower frequencies still need to be accommodated. That's where the
> regulator takes over. With a response in the 10s of microseconds, a good
> regulator won't have a problem delivering the change of current where the
> bypass caps are starting to lose effectiveness.
...snip..
> If there is a "new, better way" to power our transient-rich designs compared
> to good - local - decoupling schemes, I'd be interested to read up. As long
> as decoupling is within 1/10 the wavelength of the capacitor's effective
> frequency on a zero inductance plane, the capacitor will do it's job. As
> long as the capacitor is not degraded by the plane inductance between the
> cap and the chip, the cap will do its job. If a cap is marginalized by an
> inductance, the cap will be less effective and some analysis may be
> warranted. The numbers whould be considered.
You are preaching to the choir now!
Symon
> Symon,
>
> Answers below,
>
> Austin
>
> Symon wrote:
> > Austin,
> > PCB ground bounce? But this thread is about not having PCB power planes.
>
> It was about number of layers. A ground plane is a layer.
>
Go back and read the OP. He had a ground plane, he wanted to know if he
could get away with routing the power separately. Yes he can! Especially
with a PQ208 which has a lead frame made of little inductors on every pin! I
hope you Xilinx boys have encapsulated some bypass caps in there somewhere!
> > No-one's suggesting doing without a ground plane. That's the main
(only!)
> > weapon against ground bounce. The loop-inductance you're taking about
that
> > carries the return current is then between the FPGA and it's decoupling
> > capacitors. The ground plane ensures the power supply doesn't bounce
> > relative to the decoupled supply at the FPGA.
>
> The ground L is the bounce in the ground plane. The Vcc plane L is the
> bounce in the Vcc.
>
Assuming the ground balls/pins are connected straight to the ground plane
and if the Vcc balls/pins are coupled tightly to the ground plane via
sufficient decoupling capacitors and enough low inductance copper
track/local plane, you don't need a Vcc plane that traverses the whole
board. The current loop is between the ground plane, the FPGA, the bypass
cap. One plane can't bounce without the other if the bypass caps nail them
together!
> > If you're talking about ground bounce on the silicon, then all we PCB
> > designers can do is firmly bolt down the ground pins to the PCB ground
> > plane. A power plane, or lack thereof, isn't gonna affect ground bounce
> > after that.
> > Also, when you say in a previous post 'If you do not have both a power
and a
> > ground plane for each of these supplies, the SSO numbers must be
reduced.',
> > I'd disagree. You probably must have a ground plane, but throwing
separate
> > layers at supplies for Vcco, Vccint, Vccaux, Rocket I/O supplies is a
little
> > excessive!
>
> I said a pair of planes for each high current switching supply, namely a
> Vccint/Gnd pair, and a Vcco/Gnd pair. That makes four layers. The dual
> grounds are required to reduce the ground return inductance to something
> that is reasonable. And the vcc loop inductance. Both.
>
Not necessary. The ground layer is important, as I said later more ground
planes are good. But big planes for Vcco and Vccint are NOT necessary. Just
low inductance from the bypass caps to the FPGA power pins/balls.
> It's easier to use this methodology, and certainly easier for
> > Xilinx to support, but you can get as good results by using one or two
> > layers to share supplies locally at the FPGA.
>
> I disagree. Looking at those that succeed, vs. those who have issues, I
> see those that followed our recommendations a much happier bunch.
>
Maybe you could come up with better recommendations, then your happy bunch
might get happier and richer from the money they save on PCBs!
> We take our recommendations very seriously. We are not out to minimize
> our support, but rather to maximize our customers' successes (and our
> own in the process). To suggest a marginal power distribution system is
> just not good business! Why would we suggest that a customer 'play
> around' when we and our disti's have already run all the simulations,
> and built numerous verification, characterization, and demo pcbs to
> prove what works, and what does not work?
Fair enough. I'm sure this is true.
>
> Anyone who thinks they know better how to use our chip might get lucky,
> but often is not. Why would anyone think that they know more than we do
> about something they did not design? Surprisingly, many do think that
> they know more, and as a consequence are sometimes terribly disappointed.
>
Deep breath! I can see why you sometimes rile up Rickman! ;-) Anyway, I
count myself as someone who does know better how to use the chip in this
case, at least better than XAPP623, and I have plenty of boards to back it
up. When you get lucky every time, there's another word for it. I'm not
saying it's easy, but it's possible, and I save my company a lot of money on
PCBs by using fewer layers, fewer bypass caps, and squeezing extra
functionality onto the board. What I'm trying to do with my posts here is
help other folks understand that what Xilinx says is only one way to do it;
other ways work, and work very well. Don't get me wrong, I think Xilinx does
an excellent job, especially at support. Your recommendations enable someone
with little PCB design expertise to get it right first time. Sometimes
though, we non-Xilinx 'gentiles' can do good stuff too!
> For the introduction of V4, we had a 1Gb/s LVDS networking pcb ready to
> demo, and a memory interfaces pcb ready to demo. Those are two of the
> largest applications problems our customers face today - fast IOs and
> fast memories. If we don't know how to make it work, how would that
> make a customer feel?
>
> I always read how a vendor suggests using their device.
>
We agree on this!
> The use of the POL supplies is an experiment to validate a concept. I
> wouldn't go to product until I had proven it works (if it was my job).
>
> The same goes for using only four layers, or traces to Vcco, etc.
>
> You can also use this layer
> > for other things away from the FPGA. To do this, your decoupling must be
> > good at the FPGA, and the connection between the supply and the local
plane
> > must be able to supply the current needed.
> > You're also, IMHO, better off having multiple ground planes, and routing
the
> > power.
>
> Yes, ground is all important (more so than the Vcc's), and Vcc 'planes'
> may sometimes just be routed. It depends again on the switched currents.
>
OK, so now we agree that a routed/local planed Vcc works? You seem to
flip-flop more than a Democrat nominee! ;-) Again we agree, local plane/
routed can Vcc work fine.
> > Finally, I'd be interested in how increasing bypass capacitance can make
> > ground bounce worse in the same system, especially one with a ground
plane?
> > More energy stored?
>
> Yes, the rails don't collapse.
But if the rails collapse, ground bounce is the least of your worries. Your
design is already dead.
>
> di larger?
>
> Yes, the source impedance is lower.
>
> dt faster?
>
> Yes, lower source impedance also leads to faster transients.
>
At these high frequencies, the capacitor package size (= inductance) is the
thing that dominates the source impedance. Not the capacitance. Look at the
manufacturers data sheets. Download this and look for yourself
http://www.murata.com/designlib/mcsil.html . Above 50MHz an X5R 0402 cap has
the same impedance whether it's 56nF or 470nF. The ground bounce problem is
solely a result of poor coupling between the ground plane and the FPGA.
> Lastly, we had a case where the vias from the bypass caps where wired
> such that the L from the cap to the plane was the largest element (not
> hard to do, one tiny via each end, at the end of a flag of trace to the
> chip cap). Adding caps directly across the existing cap did absolutely
> nothing. One might conclude that the bypassing wasn't doing anything.
> But really, the L to the caps was so bad, that the caps were not doing
> anything. Little things count.
>
> Had to tell the pcb layout person to get the L out of there! (excuse the
> pun - again)
Of course, very good point. It's a constant fight against the PCB routing
tool to prevent it stripping out extra vias I add to decrease impedance.
Ah, Austin, I enjoy these chats. Even when I C your terrible puns!
Write back soon mate,
Syms. ;-)
Symon
I agree. As I said in another post in this thread, point-of-load supplies
are useful, but as long as you keep them on the board where they're used,
their position relative to the FPGA makes bugger all difference. They're low
enough in area/height/power wastage these days to place in the bits of pcb
'tundra' you often get between connectors and the like!
Cheers, Syms.
"rickman" <spamgo...@yahoo.com> wrote in message
news:416F6DB9...@yahoo.com...
Austin Lesea
See comments below,
Austin
> [snip]
>
> I think the point being made here is that bypass caps located where the
> inductance between the caps and the chip is small, the i in di/dt *is*
> significantly altered if the i being discussed is power/ground plane
> inductance.
Actually, my point is this: given some bypass arrangement, the ground
bounce does not vary if you suddenly make all the byapssing 10X better
(ie better caps, more farads). In fact, bounce may get worse because
the rails are not collapsing (anymore) externally.
>
> The regulator at the load should only help out if 1) the regulator has
> extremely fast response or 2) the current demands fluctuate at very high
> aplitudes at much lower frequencies.
Agreed. On chip, the current demand is almost instant. By the time the
local capacitance on die is exhausted, and the caps in the package are
out of charge, and the immediate external bypass caps have also given up
their electrons, the time of the current profile has been stretched. If
a regulator is fast enough, it can help. If it is too slow, it can't.
The PCI/SDRAM card I have with the POL ultra-fast transient regulators
was able to use 4 layers. Never seen anything less than 8 layers used
before. Pretty clever designers for that PDS.
-snip-
> The "Point of Load" at ti.com comes up with a DC/DC switcher module where
> "the transient response of the DC/DC converter has been
> characterized using a load transient with a di/dt of 1 A/盜." While this
> appears to be a better spec than I originally figured (for available supply
> voltages down to 3.3V, not 1.2V yet) the location could still easily be a
> couple nanoseconds of board distance away (about 10"?) and not feel the
> difference in the transient due to the di/dt of the power plane.
I believe they have all the way down to 1.0 volt available now. Check
with your TI disti. Belnix is adjustable with a resistor.
http://www.belnix.co.jp (most of the literature is in Japanese, and I
have received some recent English translations, but I am still at a
disadvantage here....)
http://focus.ti.com/docs/pr/pressrelease.jhtml?prelId=sc04126
>
> If there is a "new, better way" to power our transient-rich designs compared
> to good - local - decoupling schemes, I'd be interested to read up. As long
> as decoupling is within 1/10 the wavelength of the capacitor's effective
> frequency on a zero inductance plane, the capacitor will do it's job. As
> long as the capacitor is not degraded by the plane inductance between the
> cap and the chip, the cap will do its job. If a cap is marginalized by an
> inductance, the cap will be less effective and some analysis may be
> warranted. The numbers whould be considered.
Agree on all of the above.
The Belnix POL supply has a 50 mV MAX droop for a 5 ampere load change
(step, instant load change). Looks like it never even saw the load
change, except the IR drop happens and you see 50 mV change. They talk
about a ~100 ns time to go from 0 amperes, to supplying 5 amperes with
no overshoot or ringing of the output (beyond the normal switching noise
and the IR drop of 50 mV).
Initially, I was a non-believer, like you. Basic rules were separate
planes, minimize inductance, maximize bypass, etc. 1/10 wavelength back
of the envelope rules, etc. Then I saw a 4 layer pcb with a POL
regulator (actually, two, one for core, and one for IO) and very few
bypass caps. I had never seen a working 4 layer pcb prior to that with
PCI AND SDRAM on a 2VP20 (let alone one without a lot of caps). Just
too much current needs to be switched for BOTH PCI and SDRAM, and the
only other solution I had seen were two planes for Vccint, and two
planes for Vcco, plus a lot of bypass caps (one per power ground pin pair).
Perhaps we are both over simplifying the problem? Perhaps is it more
like a power transfer problem over a 2-D transmission line: the longer
the line, the worse the problem? By shortening the line to less than 1"
(25.4mm), the POL concept is a better solution? The output impedance of
the power supply (an active and complex value) is reflected to the load
and is kept at a much lower magnitude, which causes much less voltage
fluctuation?
Hal Murray
>do not have both a power and a ground plane for each of these supplies,
>the SSO numbers must be reduced. This also goes for simultaneously
>switching CLBs, and not just IOs. We assume a power and ground plane
>(yes that would be four layers just for power) for low inductance on the
>Vccint/Vcco.
That seems reasonable, but it's awful short on specifics.
How big does the plane have to be? Are you assuming power/gnd pairs?
If so, what spacing between the pairs? Which plane/pair needs
to be closest to the chip?
Is there a procedure for computing the SSO rules given non-optimal
power planes?
Wise-ass mode would be:
What page of the data sheet describes the details?
Let's go at it from the other direction. What are the chances of
making a solid PCI card on a 4 layer board? Assume a TQFP-208
package and assume that the PCI side is the major SSO problem
and that the routing on the non-PCI signals is easy.
I haven't done it, but I think you can get a reasonable layout
in 4 layers with a TQFP package. I'm assuming that the routing
to the signal pins from the rest of the design is easy.
(That's "reasonable" to my imagination/eyeball. Reality might
be totally different.)
The idea is that the top/bottom layers under the chip are not
needed for routing so you can fill them with copper to get
a tiny plane. It's probably not big enough to do much good,
as a plane, but it will be a solid connection for all the
appropriate power/gnd pins and bypass caps.
It would be interesting to see how good that chunk of plane
approach is compared to placing bypass caps right next to each
pair of power/ground pins (with tight routing and fat traces).
I've got a cheap modem PCI card handy. Looks like it's only
2 layers.
--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.
Austin Lesea
For specifics, please read:
http://www.support.xilinx.com/products/design_resources/highspeed_design/resource/si_power.htm
SSO guidelines are on page 23 of:
http://direct.xilinx.com/bvdocs/publications/ds099-3.pdf
Austin
Symon
news:t7-dnUVydsU...@megapath.net...
For this PCI card, I think the I/O will be your toughest problem. 32+ long
traces at 33MHz. So, I'd consider this. Assume four layers, 1, 2, 3 & 4.
FPGA mounted on layer 1. First, make layer 2 a ground plane. Underneath the
FPGA on layer 1, fill the area with copper and connect to all the Vcco pins.
Layer 3 under the FPGA should be copper flooded for Vccint. You now put a
chunky C shape around the Vccint flood on Layer 3 to route Vccaux.
Via Vccint, Vccaux and Ground to each and every required pin on the FPGA,
but keep the vias inside the square of FPGA pins, to avoid hindering routing
your I/O signals outwards on layer 1. Vcco vias can connect to anywhere on
your layer 1 mini-plane under the FPGA. If you have more than one Vcco, you
can divide up this mini plane, but try to group banks that share a Vcco
together.
On layer 4 under the FPGA, pack with bypass caps for Vcco and Vccint. (Check
XAPP623 for good advice on layout for bypass caps.) You need at least one
via for the power end of the cap, more is better, don't share vias between
caps. Flood the rest of this bit of layer 4 with ground for the bypass caps,
and use many vias to connect this layer 4 ground flood to Layer 2, your
ground plane.
Now, route your signals out on layer 1. Cram them together so that you can
fit extra bypass caps onto layer 1, for each of Vccint, Vcco, Vccaux.
As for bypass caps, use 0805s on layer 4. Use 0402s on layer 1. Via
inductance is around 1.2nH, double the capacitor inductance, so don't worry
about high frequencies on the bottom layer. In fact for a PQ208 the lead
inductance is probably around 10nH, so don't worry about all that 'spread of
capacitance values' crap, big capacitance is beautiful here!
Try it, you never know, you might be one of Austin's lucky ones! ;-)
Cheers, Syms.
glen herrmannsfeldt
Hal Murray wrote:
>>Our SSO rules assume you have dedicated planes for Vccint, Vcco. If you
>>do not have both a power and a ground plane for each of these supplies,
>>the SSO numbers must be reduced. This also goes for simultaneously
>>switching CLBs, and not just IOs. We assume a power and ground plane
>>(yes that would be four layers just for power) for low inductance on the
>>Vccint/Vcco.
> That seems reasonable, but it's awful short on specifics.
> How big does the plane have to be? Are you assuming power/gnd pairs?
> If so, what spacing between the pairs? Which plane/pair needs
> to be closest to the chip?
Inductance should also go down with the thickness of the copper,
though at some point you run into the skin effect.
Thicker copper might be cheaper than more layers.
-- glen
Symon
news:cl3k1f$kdm$1...@gnus01.u.washington.edu...
> Inductance should also go down with the thickness of the copper,
> though at some point you run into the skin effect.
> Thicker copper might be cheaper than more layers.
>
> -- glen
Glen,
Good point, but sometimes thicker copper can be a mixed blessing, the
etching process can screw up if the copper's too thick. Thinner copper
allows narrower tracks. This can let you squeeze your routing together, to
get wide tracks to where you need it. Important if you're routing power on a
routing layer. On the other hand, thick copper helps heat transfer.
Another classic engineering compromise!
Best, Syms.
Brian Davis
>
> SSO guidelines are on page 23 of:
>
> http://direct.xilinx.com/bvdocs/publications/ds099-3.pdf
>
conspicuously absent from table 23.
Other table 23 oddities:
1) Why are the SSO pin limits for those spiffy current mode
differential drivers so low, nearly the same as for the high
drive single ended I/O standards?
Answer Record 19972 still says "Because the Spartan-3 LVDS
driver is very balanced, its switching causes a negligible
amount of transient current. As a result, SSOs are not a problem."
2) Why are the table 23 SSO limits for the older voltage-mode
differential output drivers {LVPECL,BLVDS} identical to those
of the newer current-mode drivers {LVDS,LDT,RSDS} ?
3) Why do the input-only differential parallel DCI standards
show up in the SSO table?
Brian
glen herrmannsfeldt
I wrote:
>>Inductance should also go down with the thickness of the copper,
>>though at some point you run into the skin effect.
>>Thicker copper might be cheaper than more layers.
Symon wrote:
> Good point, but sometimes thicker copper can be a mixed blessing, the
> etching process can screw up if the copper's too thick. Thinner copper
> allows narrower tracks. This can let you squeeze your routing together, to
> get wide tracks to where you need it. Important if you're routing power on a
> routing layer. On the other hand, thick copper helps heat transfer.
> Another classic engineering compromise!
I was suggesting it for the power and ground planes, but I don't
know which combinations of mixing different thicknesses are allowed.
Is a four layer board built from two 2-layer boards etched separately
and then put together with an insulation layer in between? It might
be that both sides of the separate boards would have to be the same.
-- glen
Allan Herriman
<g...@ugcs.caltech.edu> wrote:
>
>I wrote:
>
>>>Inductance should also go down with the thickness of the copper,
>>>though at some point you run into the skin effect.
>>>Thicker copper might be cheaper than more layers.
>
>Symon wrote:
>
>> Good point, but sometimes thicker copper can be a mixed blessing, the
>> etching process can screw up if the copper's too thick. Thinner copper
>> allows narrower tracks. This can let you squeeze your routing together, to
>> get wide tracks to where you need it. Important if you're routing power on a
>> routing layer. On the other hand, thick copper helps heat transfer.
>> Another classic engineering compromise!
>
>I was suggesting it for the power and ground planes, but I don't
>know which combinations of mixing different thicknesses are allowed.
>
>Is a four layer board built from two 2-layer boards etched separately
They are called "cores".
>and then put together with an insulation layer in between?
That is called "prepreg".
> It might
>be that both sides of the separate boards would have to be the same.
That is usually the case, although it is possible to build up copper
thickness by plating e.g. the outer layers.
Regards,
Allan
Symon
message news:k0qan0pj35a93gnv0...@4ax.com...
>
> They are called "cores".
>
> >and then put together with an insulation layer in between?
>
> That is called "prepreg".
>
> > It might
> >be that both sides of the separate boards would have to be the same.
>
> That is usually the case, although it is possible to build up copper
> thickness by plating e.g. the outer layers.
>
> Regards,
> Allan
For a four layer board, I think it is possible to have a core, with prepreg
on either side, overlaid with foil for the outer copper layers. I use
something like this in my microvia boards, the prepreg is laserable.
Probably more expensive though.
As for whether thicker copper is useful on layers inside the board for SI
reasons, I expect the limiting factor is the via + track + lead frame
inductance to the pad, rather than the plane inductance. Good for thermal
reasons though.
Cheers, Syms.
Symon
Comments:-
"Brian Davis" <brim...@aol.com> wrote in message
news:a528ffe0.04101...@posting.google.com...
> Austin wrote:
> >
> > SSO guidelines are on page 23 of:
> >
> > http://direct.xilinx.com/bvdocs/publications/ds099-3.pdf
> >
> Except for the leaded S3 packages {VQ/TQ/PQ}, which are still
> conspicuously absent from table 23.
>
That's because the lead frame has buggered your SI before you've even
started your PCB.
> Other table 23 oddities:
>
> 1) Why are the SSO pin limits for those spiffy current mode
> differential drivers so low, nearly the same as for the high
> drive single ended I/O standards?
>
> Answer Record 19972 still says "Because the Spartan-3 LVDS
> driver is very balanced, its switching causes a negligible
> amount of transient current. As a result, SSOs are not a problem."
>
> 2) Why are the table 23 SSO limits for the older voltage-mode
> differential output drivers {LVPECL,BLVDS} identical to those
> of the newer current-mode drivers {LVDS,LDT,RSDS} ?
>
The idea is that if the voltage mode drivers switch simultaneously in
opposite directions, the current through the Vcco pins stays constant, so
the lead/trace inductance doesn't screw things up.
> 3) Why do the input-only differential parallel DCI standards
> show up in the SSO table?
>
>
> Brian
Dunno!
glen herrmannsfeldt
Symon wrote:
(after I asked about thicker copper on some layers)
> For a four layer board, I think it is possible to have a core, with prepreg
> on either side, overlaid with foil for the outer copper layers. I use
> something like this in my microvia boards, the prepreg is laserable.
> Probably more expensive though.
> As for whether thicker copper is useful on layers inside the board for SI
> reasons, I expect the limiting factor is the via + track + lead frame
> inductance to the pad, rather than the plane inductance. Good for thermal
> reasons though.
The suggestion was to improve the ground plane by making it
thicker. To reduce via inductance you need as many of them
as you can get. (Inductors in parallel.) The OP wanted a four
layer board instead of following the suggested two ground and
two power planes.
-- glen
Austin Lesea
See below,
Austin
Brian Davis wrote:
> Austin wrote:
>
>>SSO guidelines are on page 23 of:
>>
>>http://direct.xilinx.com/bvdocs/publications/ds099-3.pdf
>>
>
> Except for the leaded S3 packages {VQ/TQ/PQ}, which are still
> conspicuously absent from table 23.
>
> Other table 23 oddities:
>
> 1) Why are the SSO pin limits for those spiffy current mode
> differential drivers so low, nearly the same as for the high
> drive single ended I/O standards?
>
> Answer Record 19972 still says "Because the Spartan-3 LVDS
> driver is very balanced, its switching causes a negligible
> amount of transient current. As a result, SSOs are not a problem."
LVDS is a low current driver, but the LVPECL is two single ended drivers
with external resistors, so it has significant current.
Even LVDS has a restriction, but not nearly that of a larger driver
(more current). Unless I am missing something?
>
> 2) Why are the table 23 SSO limits for the older voltage-mode
> differential output drivers {LVPECL,BLVDS} identical to those
> of the newer current-mode drivers {LVDS,LDT,RSDS} ?
??? I'll have to ask Steve K.
>
> 3) Why do the input-only differential parallel DCI standards
> show up in the SSO table?
Because they draw current for the parallel termiantion, and the
restriction is for current drain on the Vcco/Gnd pins in the bank.
>
>
> Brian
Symon
>
> The suggestion was to improve the ground plane by making it
> thicker. To reduce via inductance you need as many of them
> as you can get. (Inductors in parallel.) The OP wanted a four
> layer board instead of following the suggested two ground and
> two power planes.
>
inductance won't change. The inductance is determined by the loop area of
the current path. Think about it, when you calculate the inductance of a
coil, you don't need to know the wire diameter, just the diameter and number
of turns.
Best, Syms.
glen herrmannsfeldt
Symon wrote:
(snip regarding decreasing inductance by thicker ground planes)
> I just realised, making it thicker will only reduce its
> resistance. Its inductance won't change. The inductance
> is determined by the loop area of the current path.
> Think about it, when you calculate the inductance of a
> coil, you don't need to know the wire diameter, just the
> diameter and number of turns.
The coil formula doesn't work so well for a ground
plane, but I do think you are right. The volume occupied
by flux is staying (about) the same. As a coil is stretched
into a straight wire its inducance decreases. Then, as the
wire gets larger it also decreases but that is because
the field spread out more.
I think, though, that more vias still decreases the
inductance until they get so close that there is a
large field overlap bewteen them.
-- glen
Hal Murray
> http://direct.xilinx.com/bvdocs/publications/ds099-3.pdf
No data for PQ-208. No data for PCI33_2 or PCI66_3. (Page 25.)
There is a note at the end of the table that says:
The numbers in this table are recommendations that assume
sound board layout practice.
But that's hard to test or measure.
I'm not trying to pick on Xilinx. Most data sheets I look at
don't even have that sort of footnote. But this is a hard
problem area. How good does "sound board layout" have to be?
How/what would you specify if you were writing the data sheet?
If you were on a jury for a big legal battle, how would you
decide if a design was "sound" enough?
Anybody got PCI running on a PQ-208 with only 4 layers? :)
Is that a silly idea?
Symon
> I think, though, that more vias still decreases the
> inductance until they get so close that there is a
> large field overlap bewteen them.
Agreed, as you said earlier "Inductors in parallel". The current is shared
between the vias. I think you're right about the total inductance increasing
as the two (say) vias get close as well, food for thought. Is that because
of the mutual inductance between the two current loops? Time to crack out a
text book!
An interesting discussion, thanks Glen!
Best, Syms.
Brian Davis
< re. the missing leaded package SSO data >
>
>That's because the lead frame has buggered your SI before
>you've even started your PCB.
>
Yes, and the poorer on-die power distribution of those
same leadframes makes adhering to those (missing) SSO
guidelines even more important than in the BGA parts.
>
>The idea is that if the voltage mode drivers switch
>simultaneously in opposite directions, the current through
>the Vcco pins stays constant, so the lead/trace inductance
>doesn't screw things up.
>
Xilinx has two flavors of differential driver:
1) the older style, voltage-mode, pseudo-differential,
switch-two-CMOS-outputs-with-an-external-resistive-attenuator
which they say doesn't balance that well :
http://www.fpga-faq.com/archives/42700.html#42709
2) the 'real' balanced current-mode drivers of the V2/V2P/S3,
which the Answer Records say is not a factor in SSO limits
So, I'd expected to see much better SSO numbers for the 'real'
LVDS drivers than for the older 'pretend' ones, but DS099, table 23,
says both types have a four-pair SSO limit per VCCO-GND pair.
Brian
Brian Davis
>
>LVDS is a low current driver, but the LVPECL is two single
>ended drivers with external resistors, so it has significant current.
>
>Even LVDS has a restriction, but not nearly that of a
>larger driver (more current). Unless I am missing something?
>
I'd also expected to see much better numbers for the
current-mode drivers, but the Spartan3 SSO table that
you referenced says otherwise:
Excerpts from DS099-3, v1.4, Table 23
SSO outputs per VCCO/GND pair
Single ended:
LVCMOS33 Fast 16mA 7 pins
LVCMOS33 Fast 24mA 3 pins
Current-mode:
LVDS_25 4 pairs (8 pins)
RSDS_25 4 pairs
Psuedo-differential:
BLVDS_25 4 pairs
LVPECL_25 4 pairs
Which lists the current mode LVDS drivers as having the
same low SSO pin limit (4 pairs) as the LVPECL drivers, and
pretty much the same pin limit as does LVCMOS33/FAST/16mA.
>
>>
>> 3) Why do the input-only differential parallel DCI standards
>> show up in the SSO table?
>
>Because they draw current for the parallel termiantion, and the
>restriction is for current drain on the Vcco/Gnd pins in the bank.
>
I'd hoped that was the reason; but since those same "4"'s were
next to every type of differential I/O in the table, I thought it
might be a block pasting error when compiling the datasheet.
Following up on this:
In "normal" operation, these on-chip DCI terminator pairs have
already been biased to 1.25 V, and experience a small balanced
input swing (~0.8V), providing some measure of terminator VCCO
current cancellation.
In this "normal" mode of operation, in the BGA packages,
they have a four pair SSO limit, possibly less for leaded parts.
But at post-configuration DCI startup, these terminators all
switch simultaneously, unbalanced, from full stop to 1.25 V
Given that this unbalanced, larger swing should have poorer SSO
limits than the "normal" operation, that's why I was concerned over
on that other thread about using LVDS_25_DCI in the leaded packages.
Brian
Symon
>
> < re. the missing leaded package SSO data >
>>
>>That's because the lead frame has buggered your SI before
>>you've even started your PCB.
>>
>
> Yes, and the poorer on-die power distribution of those
> same leadframes makes adhering to those (missing) SSO
> guidelines even more important than in the BGA parts.
>
V. good point. I wonder, do the IBIS models include the lead frame?
>>
>>The idea is that if the voltage mode drivers switch
>>simultaneously in opposite directions, the current through
>>the Vcco pins stays constant, so the lead/trace inductance
>>doesn't screw things up.
>>
>
> Xilinx has two flavors of differential driver:
>
> 1) the older style, voltage-mode, pseudo-differential,
> switch-two-CMOS-outputs-with-an-external-resistive-attenuator
>
> which they say doesn't balance that well :
> http://www.fpga-faq.com/archives/42700.html#42709
>
> 2) the 'real' balanced current-mode drivers of the V2/V2P/S3,
> which the Answer Records say is not a factor in SSO limits
>
> So, I'd expected to see much better SSO numbers for the 'real'
> LVDS drivers than for the older 'pretend' ones, but DS099, table 23,
> says both types have a four-pair SSO limit per VCCO-GND pair.
>
>
> Brian
I got the difference between the two types, but failed to realise that they
didn't balance so well. Thanks for the link you posted to Bob and Austin's
exchange, I'm thinking again.
I guess I'm very cynical, I think the "25 ps to 125 ps" time from the pad to
the pin is a red herring. The synchronicity of the IOBs outputs switching on
the die is what's important.
Maybe the 'gate' or drive capacitance of the output transistors added to the
bounce? Maybe a tiny bit! I guess that leaves the crossover current, but how
long does that last? I thought the output structure stopped that happening.
CMOS, right? And how did they measure it? Hmmm!
Cheers, Syms.
Hal Murray
>started your PCB.
Then why does Xilinx sell the chips? They must be good for something.
Maybe there is a comment in some ap-note that says not to bother
trying to implement PCI in a PQ-208 type package. (and explaining
why) Or maybe it takes 8 layers, or ...
I haven't seen anything like that, but I haven't looked carefully
and nobody has mentioned anything like that yet in this discussion.
"Don't do that" might be the right answer.
Brian Davis
>
>I wonder, do the IBIS models include the lead frame?
>
Earlier versions of the S3 IBIS files used the SAME package
model for ALL packages, from BGA through PQFP; the IBIS file
had tiny entries for package parasitics, and Xilinx suggested
a user-added Tline model to model the pin:
uncoupled 65 ohm transmission line, 25-100 ps delay
from :
http://direct.xilinx.com/bvdocs/appnotes/xapp475.pdf
Now, if what you're modeling is a transmission line, or
behaves like one at the edge rates of interest, a Tline
model is more appropriate than a single element lumped
approximation; but to model a conventional leadframe package
with an UNCOUPLED** Tline model seems rather optimistic.
Looking again today, the latest version (2.6) of the S3 IBIS
files now has lumped parasitics for some of the leaded packages
( PQ208 and TQFP144, but not the VQ100 ). Note: XAPP475 has not
yet been updated to address this modeling change.
The other concern I have with the Xilinx IBIS models is
that they're still using an ancient version of IBIS (2.1),
which doesn't support some of the newer IBIS features such
as differential input parasitics. ( Which explains the lack
of IBIS models for the _DT terminators in the V2Pro )
** I don't believe IBIS 2.1 supports modeling of pin-pin coupling
Brian
Symon
<snipped very informative stuff>
>
> The other concern I have with the Xilinx IBIS models is
> that they're still using an ancient version of IBIS (2.1),
> which doesn't support some of the newer IBIS features such
> as differential input parasitics. ( Which explains the lack
> of IBIS models for the _DT terminators in the V2Pro )
I see in XAPP475 they say that "Unfortunately, IBIS 3.2 still is not widely
supported by simulators.". It wouldn't hurt to publish new IBIS3.2 or even
4.0 files alongside the old ones though!
Thanks for a very informative post, much appreciated.
Best, Syms.
Austin Lesea
IBIS 4.0 is now out for bid for the "golden parser."
Without a "golden parser", no one can say they adhere to the standard.
The last golden parser was back in the IBIS 1.2 days, so that is all
anyone can lay claim to.
If you claim something more than that, you are not being entirely
honest. Small errors in the IBIS file get rejected by various tools,
and support mushrooms.
As well, not everyone implemented the changes in IBIS 2, 3.... the same
way, or the simulators implementations were also not identical....
We have 200,000+ seats of software out there, and trying to blaze a new
trail for IBIS is like pushing tons of wet spaghetti (hard work, and not
very satisfying).
We are actively looking at when to fold in the new IBIS, but only after
it is supported by the tools that allow us to succeed. Until then, we
use what we have got, which includes the encrypted hspice versions for
folks that have to have the "answer."
For the MGTs, no one can say if IBIS is adequate or not for differential
signals at 10 Gbs, so we are sticking to methods that we know work. We
do know that behavioral models are really fast, but also really
inaccurate. If someone has a complete backplane simulation with
extracted pcb parasitics (s parameters, complex lossy t-lines,
connectors, pre-emphasis transmitter and adaptive receiver, etc.) that
is within 5% of the behavioral model, I'd like to know how the miracle
occurred.
Austin
Brian Drummond
wrote:
What you can do, though, is play with the thickness of the prepreg. Make
it thin enough and you increase the capacitance between ground and power
planes. Not to a very high value, granted, but connected to the planes
by a _very_ low inductance!
- Brian
Brian Davis
>
> I see in XAPP475 they say that "Unfortunately, IBIS 3.2
> still is not widely supported by simulators.".
>
yesterday to find the TLine parameters.
I was actually thinking of this sentence from Answer Record
#19320 when I griped about Xilinx still using IBIS 2.1:
"We do not have an IBIS model for LVDS_25_DT, as
the IBIS specification does not provide a mechanism
for representing the true differential termination"
It's been I while since I read the IBIS specs, but I believe
it was IBIS 3.x which added support for modeling a differential
terminator, instead of having to bury single-ended terminator
currents in the GND/VCC clamp table.
> It wouldn't hurt to publish new IBIS3.2 or even 4.0 files
> alongside the old ones though!
My interest in having data available in one of the newer
IBIS versions is not to actually use them in an IBIS simulator,
but to have {almost} human-readable documentation of the
differential package and I/O parasitics, which Xilinx doesn't
currently publish in any other form.
I suspect if you use the differential I/O standards, and then
tie adjacent I/O pins as strong drivers to GND(VCCO), you can
establish a nice GND S+ S- GND(VCCO) pinout in a leaded package
and have a good shot at doing extremely fast I/O in an el-cheapo
package.
And I'd love to see a small S3 sold in one of the enhanced
VQFP ground-paddle packages, for both thermal and electrical
reasons, especially if done with a G S+ S- G pinout.
>
>Thanks for a very informative post, much appreciated
>
As were yours, thanks - I've been building 4-6 layer boards
with FPGA's powered from localized plane fills, as you describe,
for many years and generations of FPGA. Keeping the 'dirty' FPGA
power plane localized in such a fashion also helps in RF/mixed
signal board layouts.
I took a look at building a simple first or second order SPICE
package model of the leaded S3 parts a few months ago, but there
wasn't any package data available in the IBIS files; if I get a
chance to take another crack at it, I'll post some LTspice files.
And if anyone out there has built a test fixture and made
either differential TDR or VNA measurements on some of the S3
leaded packages, I'd love to see some real world data to help
model the pin-pin coupling for a G S+ S- G pinout :)
Brian