External Cloking of Altera MAX 7000S
Moussa A. Ba
finished simulating my first FPGA design. The simulated is based on a
4Mhz clock. After burning the circuit on the chip and supplying my
external clock through a 4 Mhz crystal, the clock gets totally messed up
as soon as it is connected to the fpga clock input, am I suffering from
loading problem? Is there any other way to provide a reliable clock to
the system. By the way, the board I am using is the UP1 board
university program.
Thank you in advance
Brad Ree
actually an EPLD (Altera terms) or CPLD(Xilinx terms). The reason for this
is that this device has a PLD structure, which is the AND/OR array feeding
into registers.
These EPLDs and FPGAs can not work with a crystal as the clock source. You
should use an oscillator for the clock. I am not familiar with the UP1
board, but would expect that there would be a location for an oscillator.
Andy Peters
>Good day, I am very new to FPGA design so excuse my ignorance. I just
>finished simulating my first FPGA design. The simulated is based on a
>4Mhz clock. After burning the circuit on the chip and supplying my
>external clock through a 4 Mhz crystal, the clock gets totally messed up
>as soon as it is connected to the fpga clock input, am I suffering from
>loading problem? Is there any other way to provide a reliable clock to
>the system. By the way, the board I am using is the UP1 board
>university program.
You can't use a crystal by itself, like you can on some microcontrollers.
Crystals do not have TTL (or CMOS) outputs. You need to buffer it (the
common trick is to use unbuffered CMOS inverters; I forget the part number).
Save yourself some grief and buy a 4 MHz TTL-out oscillator.
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"Creation Science" is oxymoronic.
Moussa Ba
crystal oscillator. And I still get a messed up signal as soon as I connect the
clock to the clock input of the MAX chip.
P.S.: I am an alumni of University of Arizona, currently in Maryland, how is
Tucson?
Mike
Moussa Ba wrote in message <37FD1D45...@eng.umd.edu>...
>Thank you for your reply. I forgot to mention in my email that I did use a
TTL
>crystal oscillator. And I still get a messed up signal as soon as I
connect the
>
>clock to the clock input of the MAX chip.
>
Is it possible that you connect your clock to a wrong pin? Check how your
pins were routed in your .rpt file. It sounds like you are connecting your
clock to a pin configured as an output.
Mikhail Matusov
Moussa Ba
MAX7000S as well as a FLEX10K chip. I did notice that on the pinout of the
MAX7000S it had a bunch of VCCIO, VCCINT and GND pins. In my pin description
file it mentions that these pins have to be connected to 5.0,5.0 and GND
respectively. I assumed that these pins were directly driven by the on-board
power supply. Is my assumption wrong? I did test out the pins and they provide
no Voltage. Do I have to provide that voltage?
Moussa
Andy Peters
>The board I am using is the University Program Altera board that features a
>MAX7000S as well as a FLEX10K chip. I did notice that on the pinout of the
>MAX7000S it had a bunch of VCCIO, VCCINT and GND pins. In my pin
description
>file it mentions that these pins have to be connected to 5.0,5.0 and GND
>respectively. I assumed that these pins were directly driven by the
on-board
>power supply. Is my assumption wrong? I did test out the pins and they
provide
>no Voltage. Do I have to provide that voltage?
VCCIO and VCCINT are the chip's power supply voltage inputs. You need to
connect them to a +5V supply. The board should have some sort of
power-supply input (otherwise, it's not going to do anything interesting!).
tucson is gorgeous this time of year...
davez...@my-deja.com
are the I/O voltage pins. VCCINT pins are the internal logic power
pins. If your design use 5V only both of them will be connected to 5V.
If you want interface to 3.3V parts, then you need connect VCCIO to
3.3V supply.
In article <37FE7BBC...@eng.umd.edu>,
Moussa Ba <ba...@eng.umd.edu> wrote:
> The board I am using is the University Program Altera board that
features a
> MAX7000S as well as a FLEX10K chip. I did notice that on the pinout
of the
> MAX7000S it had a bunch of VCCIO, VCCINT and GND pins. In my pin
description
> file it mentions that these pins have to be connected to 5.0,5.0 and
GND
> respectively. I assumed that these pins were directly driven by the
on-board
> power supply. Is my assumption wrong? I did test out the pins and
they provide
> no Voltage. Do I have to provide that voltage?
>
> Moussa
> Mike wrote:
>
> > Moussa Ba wrote in message <37FD1D45...@eng.umd.edu>...
> > >Thank you for your reply. I forgot to mention in my email that I
did use a
> > TTL
> > >crystal oscillator. And I still get a messed up signal as soon as
I
> > connect the
> > >
> > >clock to the clock input of the MAX chip.
> > >
> >
> > Is it possible that you connect your clock to a wrong pin? Check
how your
> > pins were routed in your .rpt file. It sounds like you are
connecting your
> > clock to a pin configured as an output.
> >
> > Mikhail Matusov
>
>
Sent via Deja.com http://www.deja.com/
Before you buy.
Edward Moore
The Klingons are the only people able to cloak a MAX device, and it requires
a quantum hilarity to power it.
Or do I mean the ROMulans ?.
--
Edward Moore