comp.arch.fpga Google Group

Re: ANNOUNCE: TimingAnalyzer version beta 0.87

kennheinr...@sympatico.ca — Sun, 20 Jul 2008 18:43:28 UT

Anyone who (1) develops a tool that is useful, at least in principal,
to the majority of people doing digital design, (2) listens to and
applies feedback derived from these postings, and (3) offers a free
version (limited or not), would seem to be entirely justified in
posting to at least those few groups I've seen these posts in

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Re: Change clock domain for FIFO ...

al...@sbcglobal.net (Peter Alfke) — Sun, 20 Jul 2008 17:33:46 UT

A dual-clock (also called asynchronous FIFO) is complex inside because
of the flag control, but is very easy to use:
The input port and the output port are completely separate. You put in
data at any rate, and you pull it out at any other rare you desire.
There is a Full flag that tells you tonstop writing into it, and there

Re: ANNOUNCE: TimingAnalyzer version beta 0.87

j...@ieee.org (Jerry Avins) — Sun, 20 Jul 2008 17:29:23 UT

...
Asking opinions can be a marketing ploy. Political and public-interest
organizations often include a questionnaire with low-key appeals for a
donation. Dan is different. He has actually acted on the suggestions he
got, to the point that he has produced new (and improved) versions that
incorporate most of them. In fact, those new versions account for the

Re: ANNOUNCE: TimingAnalyzer version beta 0.87

j...@ieee.org (Jerry Avins) — Sun, 20 Jul 2008 17:21:48 UT

...
Thanks for putting that more clearly than I could.
Jerry

Re: ANNOUNCE: TimingAnalyzer version beta 0.87

cbfalco...@yahoo.com (CBFalconer) — Sun, 20 Jul 2008 14:27:12 UT

No, I admit I didn't. I have limited interest in such a utility.

Re: ANNOUNCE: TimingAnalyzer version beta 0.87

j...@ieee.org (Jerry Avins) — Sun, 20 Jul 2008 17:02:38 UT

...
Years ago, I bought ($10) a very nice interactive star map program
called SkyGlobe for DOS. A few years later, I got a free upgrade for
Windows. I still use it. This stuff is shareware, and I don't think of
it as commercial. I put TimingAnalyzer in the same category. I hope it
hets to be as polished.

Re: Change clock domain for FIFO ...

secure...@gmail.com — Sun, 20 Jul 2008 16:57:00 UT

Thanks KJ,
I do not search 'dual clock fifo', thanks. But i search a interface
code for place a external clock + data to 'dual clock fifo' for first
domain clock. The dual clock fifo is ready. I still want to link the
'Tuner'.
Regards,
Kappa.

Re: Change clock domain for FIFO ...

kkjenni...@sbcglobal.net (KJ) — Sun, 20 Jul 2008 16:48:50 UT

1. Search the web site of whatever vendor you plan to implement this in for
a dual clock fifo.
2. Instantiate that component
Alternatively, google for
- lpm_fifo_dc (dual clock fifo) and you should be able to run across the
source code. Altera's code is in a file called 220model.vhd which you get

Re: Change clock domain for FIFO ...

secure...@gmail.com — Sun, 20 Jul 2008 16:36:41 UT

Hi,
I am okay. Sample with my clock against the rising clock of tuner and
this enabled the writing of FIFO ?
Some code ?
Regards,
Kappa.

Re: Change clock domain for FIFO ...

secure...@gmail.com — Sun, 20 Jul 2008 16:34:13 UT

Thanks Lorenz,
I use a Virtex-4 SX35 and Spartan-3E 500 ...
Exactly. The clock input can vary from a minimum of 125 Hz to a
maximum of 11250000 Hz. Some problem could be the first to power up.
Any idea ?
Regards,
Kappa

Re: Change clock domain for FIFO ...

n...@puntnl.niks (Nico Coesel) — Sun, 20 Jul 2008 16:02:46 UT

This is sort of a text book example. The easiest way though is to
clock the FIFO at the highest frequency and create clock domain
transfer logic at the interface with the lowest frequency. This way
you keep your FIFO at one clock frequency and put the tricky part in a
relative simple piece of logic.

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Re: ANNOUNCE: TimingAnalyzer version beta 0.87

gnu...@gmail.com (rickman) — Sun, 20 Jul 2008 15:30:51 UT

If I understand your post correctly, you are making two points. The
first is that since it is impossible to stop all spam, that we should
not try to stop *any* spam posts, is that correct? That is, when
otherwise reputable companies use spam to promote their products, we
should just shrug our shoulders and consider this part of the Internet

Re: Change clock domain for FIFO ...

lorenz.k...@uni-ulm.de (Lorenz Kolb) — Sun, 20 Jul 2008 14:57:48 UT

That sounds quite reasonable as this is a typical usage of a fifo
(switching between clock domains).
> Do you have an example of VHDL code that I could use ?
Well depending on the device you use there might be some small hacks to
think of (e.g. Virtex-4 BRAMs in FIFO mode need at least 3 cycles of the