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Format of Actel's SVF files
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johanne...@gmx.de
Aug 29, 2008, 8:37:33 AM8/29/08
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Hi everyone,
I have a PA3 device on a board where I want to make a quick blank
check to decide if it's neccesary to program or not to program. I use
a JTAG system from Goepel that uses SVF files generated by Actel. The
guy who designed the FPGA can't get me a 'blank check' SVF or a
shortened verify.
What I try now is to delete as much as possible from the verify SVF I
have to keep the time short but I'm a bit lost how to do the
manipulations right. My idea is to use just 1-5 of the 2300 rows for
the verify the fpga has.
Any ideas?
Thanks,
Johannes
I have a PA3 device on a board where I want to make a quick blank
check to decide if it's neccesary to program or not to program. I use
a JTAG system from Goepel that uses SVF files generated by Actel. The
guy who designed the FPGA can't get me a 'blank check' SVF or a
shortened verify.
What I try now is to delete as much as possible from the verify SVF I
have to keep the time short but I'm a bit lost how to do the
manipulations right. My idea is to use just 1-5 of the 2300 rows for
the verify the fpga has.
Any ideas?
Thanks,
Johannes
Antti
Aug 29, 2008, 9:40:15 AM8/29/08
to
use USERCODE
and verify only that
Antti
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