AES decryption (ASIC)
swissi...@gmail.com
To implement an AES decryption (CBC mode ) algorithm in ASIC , what
would be the best way to do it ? i mean among these architectures
which one do you choose and why :
* Basic iterative architecture
* Partial loop unrolling
* full loop unrolling
* Partia outer-round pipelining
* Full outerround pipelining
* Inner-round pipelining
* Partial mixed innerand outerroundpipelining
* Full mixed inner- and outer-round pipelining
* other ...
Jon Beniston
What process are you using and what are your power / area / bandwidth
requirements.
Jon
dajjou
Thank you jon ,
In fact i need to know the architecture of such algorithm ( AES 256
decryption CBC mode) inside an ASIC that i don't know anything about
it (area ,bandwith ...).
my question is how many possibilities to implement this algorithm ?
could we fix all possibilities ?
Jon Beniston
> Thank you jon ,
> In fact i need to know the architecture of such algorithm ( AES 256
> decryption CBC mode) inside an ASIC that i don't know anything about
> it (area ,bandwith ...).
> my question is how many possibilities to implement this algorithm ?
You can implement AES in many different ways. Which is right for you
will depend upon what your requirements are.
Jon
arsonper...@gmail.com
Keep in that you'll only need to do the roundkey expansion once for
each chain of CBC operations, so if you can compute that and store it
in a register file of some sort. If you already have existing AES
encryption IP, be sure to look at 5.3.5 of FIPS-197. You may be able
to implement the decryption operation by simply changing the internal
blocks to their inverse functions.
Mike Treseler
Is this multiple choice or an essay question?
Will this be on the test?
Thomas Stanka
the first is the smallest and slowest. You choose it, when small area
is more important than throughput. I'm no AES-Expert, but full loop
unrolling means you need ~14 times the area and gain a bit less then
14 times throughput.
Ask your self what you need.
bye Thomas