problem fpga aera optimization

[bjzh...@gmail.com]

Hi,recently,I receive a task to add another new function to the
project previously finished,but the problem is that the old project
have consume about 5K of total 7K LUTs,and the new function need about
2.5K LUTs,so I must optimize the old logic but I have no idea,can
someone give some advice about the logic optimization,the chip is
spartan3,the synthesis tool is synplify9.4 pro,P&R tool is 10.1.

[Gabor]

You might want to look at the block RAM utilization and see if
you can gain anything by using additional block RAM's (if
available) to replace some of the logic.

[d_s_klein]

You need 7.5K, you have 7.0 - welcome to the real world.

You will need to rewrite/remove some logic - Synplify, ISE, etc -
these are not the tools that will do that.

I suggest 'emacs' and 'modelsim' - that's what I would use.

RK

[Oscar Almer]

On Wed, 4 Nov 2009 07:43:32 -0800 (PST)
d_s_klein <d_s_...@yahoo.com> wrote:

> You need 7.5K, you have 7.0 - welcome to the real world.

You will probably also want to aim for less than 100% usage - timing
constraints tends to get very hard to meet the higher the utilization
is. I've seen any number of exponential graphs, all indicating that
around 75-85% utilization it gets iffy.

Of course, if the design doesn't need to be clocked particularly
high, you'd be fine with higher utilization.

//Oscar

[John Adair]

There are a lot of ways to achieve logic size reductions I have seen
reductions of 30-50% on customer designs achieved here with a lot of
expert knowledge but does depend on the original design. So starting
with the some simple things:

(1) Play with state machine encoding selection - changing a 1-hot to
sequential can save a lot.
(2) Play with speed and size settings. They don't always do exactly as
the name suggests.
(3) In the Xilinx mapping make sure you have setting to use i/o
registers.
(4) Consider SRL16 to replace shift register chains. Removing a reset
term will often let the synthesiser do this for you. Can save a lot.

Beyond these simply looking at how the design is implemented and
restructuring can save more but that is a much more complex subject.
Try the simple first as you don't need much.

John Adair
Enterpoint Ltd. - Home of Craignell. The DIL FPGA Module.

[Kastil Jan]

Hi,
you did not mentioned how much resources is consumed if you compile the
new design. Sometimes the sythesis and p&r tools are able to do wanderfull
optimalizations jobs. So I would suggest (maybe you have already done),
that you first implement the design and look if the constraints are met.
If not, than I would try to use PlanAhead or something to run several
optimalization strategies through night to see if map and par will be able
to do the job. Do not forget about alowing the global optimalization in
the map.

Also remember that p&r works little differently on the full designs and on
the designs with a free. So it is not true that 5+2.5 = 7.5A

Jan

[Martin Thompson]

"bjzh...@gmail.com" <bjzh...@gmail.com> writes:

If you are unfamiliar with the project, it can help to know which parts
of the current design are using the most resources, so you know where to
target your optimisations.

I wrote a tool to help with visualising this (for a design I had to chop
in half to fit the new stuff in). You can read about it here:

http://www.conekt.net/fpgaoptim.html

Drop me an email if you want a download link...

Cheers,
Martin

--
martin.j...@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

[Muthu]

On Nov 5, 11:55 am, Kastil Jan <ikas...@stud.fit.vutbr.cz> wrote:
> Hi,
> you did not mentioned how much resources is consumed if you compile the
> new design. Sometimes the sythesis and p&r tools are able to do wanderfull
> optimalizations jobs. So I would suggest (maybe you have already done),
> that you first implement the design and look if the constraints are met.
> If not, than I would try to use PlanAhead or something to run several
> optimalization strategies through night to see if map and par will be able
> to do the job. Do not forget about alowing the global optimalization in
> the map.
>
> Also remember that p&r works little differently on the full designs and on
> the designs with a free. So it is not true that 5+2.5 = 7.5A
>
> Jan
>

>   On Wed, 4 Nov 2009, bjzhan...@gmail.com wrote:
>
> > Hi,recently,I receive a task to add another new function to the
> > project previously finished,but the problem is that the old project
> > have consume about 5K of total 7K LUTs,and the new function need about
> > 2.5K LUTs,so I must optimize the old logic but I have no idea,can
> > someone give some advice about the logic optimization,the chip is
> > spartan3,the synthesis tool is synplify9.4 pro,P&R tool is 10.1.

I agree with Jan. I have experienced this. Many times the Slices were
not fully used. So, the additional logics can use the existing slice
and the overall resource count will be less than 7.5K.

[bjzh...@gmail.com]

> > spartan3,the synthesis tool is synplify9.4 pro,P&R tool is 10.1.- 隐藏被引用文字 -
>
> - 显示引用的文字 -

Thanks,I have done all the things listed above,but when map the
design,log file indicate that not all FFs can be mapped,the total FFs
is 5K,total LUTs is 6k,but the total slice is more than 7K,so I think
not all the logic cell contain both FF and LUT,some LE contains only
LUT and some LE contains only FF,What I want to know is that in what
circunstance the LE can't contain both the FF and LUT,What should I
consider when I do the plan and select the right device number,and
when I add new function(as 2K LUT 1K FFs), how should I know if the
old project can add the new function(left 3k lut free and 1k ff free
but )?I want to know the more detail ,pls give me some advice or wp,3x.