RLC package parasitics

[kislo]

In the IBIS model i can find the package parasitics R_pkg, L_pkg and
C_pkg ... but what does these values represent? is it the total
parasitics of the entire pins of the package? is it for single pins of
the package?

[David Spencer]

"kislo" <kis...@student.sdu.dk> wrote in message
news:bbc75873-123f-4c0e...@b1g2000hsg.googlegroups.com...

http://vhdl.org/pub/ibis/ver4.2/ver4_2.pdf

[austin]

kislo,

The parasitics are the extracted RLC from the transmission lines in the
package. The package specific models have a min, typ, and max value.

The simulators take the RLC, and create a multi-section t-line from
pi-models based on these values (as it is not an R, and L, and a C).

For per pin parasitics, you disable the RLC (comment it out of the
model) and replace it with the package t-line of the proper length in
your simulation.

Xilinx supports package maps of per pin time delay, or per pin t-line
length to a package ball in 5mm 'buckets'. This length is also used by
those who are designing wide buses which must arrive all at the same
time. The concern is that for the highest speed buses we need to go to
1 mm resolution. Perhaps we do. In any event, if you really need the
exact length, you may request this from your Xilinx FAE.

Austin