Active-HDL simulator recompile... or not recompiling

[rickman]

I have been using Active-HDL (AHDL) for over a year now and I am
pretty happy with it. For one thing, it doesn't have the apparently
unfix-able, tool crashing, memory leak that every version of Modelsim
I have ever used seems to have.

I find that as I go through the edit-compile-simulate cycle I use the
toolbar buttons to 1) Restart the simulation, 2) recompile all modules
3) use a right click menu to clear the waveform display. But this
mostly does not actually recompile the code or does not recompile it
fully or does not use the recompiled code. After a source change I
have to run around this cycle twice to get the new code to actually
simulate.

What am I missing? I find that if I *don't* recompile and try to run
again, I get a dialog telling me the source is out of date and I can
recompile if I want. If I say yes, it recompiles and *always* seems
to do it correctly.

I would say that was a clue, but I am not being Hercule Poirot today
it seems.

Rick

[gabor]

Don't know about AHDL, but in ModelSim you definitely need to
do steps 1 and 2 in the reverse error to use the newly
recompiled code. The last time I touched Aldec stuff was
when Xilinx Foundation (4.1 and prior) had it bundled together.

Regards,
Gabor

[rickman]

Duh! Now that you say that, I see how obvious that is. I guess
pushing buttons makes it so easy to forget what is going on. I was
thinking that restart the simulation was ending it and the compile
would start the new one, but obviously "restart" means restart! Would
have thought that would happen???

That is what happens when you don't use a tool for a few months. I do
still remember which end of the hammer to hold...

Thanks,

Rick

[MM]

Rick,

> 2) recompile all modules

Sometimes "recompile all modules" may not work first time if the order of
compilation has not been set properly.

/Mikhail

[Mike Treseler]

MM wrote:

> Sometimes "recompile all modules" may not work first time if the order of
> compilation has not been set properly.

With vhdl-mode,

right-click, Speedbar, Generate Makefile
right-click, Speedbar, Make

does the trick.

-- Mike Treseler

[Brian Drummond]

because VHDL sources contain all the information necessary to determine the (or
rather, a ) correct order of compilation, and vhdl-mode simply translates it.

There is really no excuse for other tools being unable to do the same.

(Mixed language projects may be another matter)

- Brian

[rickman]

On Jul 4, 7:19 am, Brian Drummond <brian_drumm...@btconnect.com>
wrote:

The Lattice software has a mode of compiling that evaluates the order
to compile the modules and remembers it for subsequent builds. That
was not an issue with my build. I was just restarting my simulation
before I recompiled.

Rick