Virtex and PCI 5V?

[wq...@yahoo.com]

Xilinx claims that Virtex is compliant with PCI 5V.
Virtex is 3.3V IO, without 5V clamping diodes on its IO pins, which is
required by PCI Spec.
Somebody comment it?

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[Peter Alfke]

wq...@yahoo.com wrote:

> Xilinx claims that Virtex is compliant with PCI 5V.
> Virtex is 3.3V IO, without 5V clamping diodes on its IO pins, which is
> required by PCI Spec.
> Somebody comment it?
>

Last time I looked at the PCI specification,
5V PCI explicitly did NOT require a diode clamp to 5 V,
( 3V PCI, on the other hand, demands such a diode.)

Peter Alfke, Xilinx Applications

[Jim McManus]

The required clamping for 5 V PCI is the lower clamp diode. This is a
standard feature for most CMOS devices. The upper clamp diode is
optional for 5 V PCI signaling environment.

From the V2.2 PCI Spec, page 120 (5 V signaling):
"Inputs are required to be clamped to ground. Clamps to the 5V rail are
optional, but may be needed to protect 3.3V input devices."

The PCI spec recommends it under the assumption that this is the best
way to protect a 3.3 V device against the up to 11 V overshoot of the 5
V PCI bus.

From the PCI V2.2 Specification, page 114:
"While the primary goal of the PCI 5V to 3.3V transition strategy is to
spare vendors the burden and expense of implementing 3.3V parts that are
"5V tolerant," such parts are not excluded."

But Xilinx 3.3 V parts are 5 V PCI tolerant without an upper clamp
diode; the XLA, SpartanXL, and Virtex FPGA families are certified to
withstand this overshoot. In fact, we require you to turn off the upper
clamp diode when using this in a 5 V PCI system. We do not certify these
devices to take 11 V *DC*; only that they will withstand the 5 V PCI AC
specification.

Jim McManus
Xilinx PCI Applications Engineer

wq...@yahoo.com wrote:
>
> Xilinx claims that Virtex is compliant with PCI 5V.
> Virtex is 3.3V IO, without 5V clamping diodes on its IO pins, which is
> required by PCI Spec.
> Somebody comment it?
>