DDR RAM timing contraints

[pwie42]

hei list,

i am working on a DDR-Ram controller for the ml401 board from xilinx.
the controller i am using is generated by the MIG tool provided by
xilinx. I have adapted this design to be used with the ml401, and
everything works fine in the simulation,

BUT: when i am running a backannotated sdf simulation of the PAR model
i get some VITAL timing error from one in die dqs input out block
located FF which looks something like this:

# ** Warning: /X_FF SETUP Low VIOLATION ON I WITH RESPECT TO CLK;
# Expected := 0.108 ns; Observed := 0.07 ns; At : 285545.237 ns
# Time: 285545237 ps Iteration: 3
Instance: /mem_interface_top_tb/dut/
main_00_top_00_iobs_00_data_path_iobs_00_v4_dqs_iob3_dqs_pipe1

a setup time violation in the X_FF primitve! so i tried to constraint
the design properly to tell the par tools to take care of this:
first of all i was following the quide provided by:
http://www.xilinx.com/xlnx/xil_ans_display.jsp?iCountryID=1&iLanguageID=1&getPagePath=12819&BV_SessionID=@@@@1652334992.1190471362@@@@&BV_EngineID=ccceaddllfjgmlecefeceihdffhdfkf.0

#constrains the main clock after the DCM
NET "CLK_0" TNM_NET = "clk0_grp"; # Group FFs that are clocked by DCM
CLK0 output
TIMESPEC "TS01" = PERIOD "clk0_grp" 10 ns HIGH 50%;

#reates the timing group that contains all the DDR input pads:
#INST cntrl0_DDR_DQ[*] TNM="IN_DDR_grp";
INST cntrl0_DDR_DQS[3] TNM="IN_DDR_grp";

#create the separate timing groups for the rising and falling-edge
registers.
TIMEGRP "DDRInRisingGrp" = RISING "clk0_grp";
TIMEGRP "DDRInFallingGrp" = FALLING "clk0_grp";

#we apply the OFFSET IN BEFORE constraint to the rising edge timing
group -
#the data to be clocked on the rising edge has a setup time of 2.5ns
before the rising edge
TIMEGRP "IN_DDR_grp" OFFSET = IN 2.5 ns BEFORE "sysclk_in" TIMEGRP
"DDRInRisingGrp";
TIMEGRP "IN_DDR_grp" OFFSET = IN -2.5 ns BEFORE "sysclk_in" TIMEGRP
"DDRInFallingGrp";

without any results, i was also trying to run the design at a lower
clk speed of 50Mhz -> no results... btw. the synthesis tools reports
that speeds up to 200 Mhz are possible. i would like to run the design
with a 100Mhz clk,

i also tryed to constrain the net with an AFTER constraint:

NET "main_00/tNET "sysclk_in" TNM_NET = "sysclk_in";
TIMESPEC TS_sysclk_in = PERIOD "sysclk_in" 10 ns HIGH 50%;

NET "main_00/top_00/iobs_00/data_path_iobs_00/v4_dqs_iob3/DDR_DQS"
OFFSET=IN 1 ns AFTER "sysclk_in";
without any results.

i also tryed a FROM TO constraint like this:
TIMESPEC TS_offset = FROM "clk0_grp" to "IN_DDR_grp" 2.781 ns;
without any results.

with all the tries i have done so far, not even the time of the
violation changes.

has anyone please some suggestions what else i could try, or how this
has to be done?

thanks a lot in advance,

paul