I'm creating a dual-port ROM, both sides are the same: 7-bit address,
32-bit data.
Very simple ISE 13.3 project can be downloaded from here:
http://www.mediafire.com/?xmf55vwdb14qvbf
Both Implementing and Generating the bit file gives warning like this
one:
PhysDesignRules:812 - Dangling pin <DIA0>
all the way from DIA0 to DIA31.
> I'm creating a dual-port ROM, both sides are the same: 7-bit address,
> 32-bit data.
> Very simple ISE 13.3 project can be downloaded from here:
> http://www.mediafire.com/?xmf55vwdb14qvbf >
> Both Implementing and Generating the bit file gives warning like this
> one:
> PhysDesignRules:812 - Dangling pin<DIA0>
> all the way from DIA0 to DIA31.
I think this is probably OK. Have you simulated your design and/or seen that it works as you expect in hardware?
I have often seen similar warnings for unused address lines on block RAMs for Microblaze or PPC designs. The ROM and RAM are made from the same Block RAM primitives, so the same connection lines are there, even if not implemented.
Maybe somebody else will chime in with a more concrete answer though.
> > I'm creating a dual-port ROM, both sides are the same: 7-bit address,
> > 32-bit data.
> > Very simple ISE 13.3 project can be downloaded from here:
> >http://www.mediafire.com/?xmf55vwdb14qvbf > >
> > Both Implementing and Generating the bit file gives warning like this
> > one:
> > PhysDesignRules:812 - Dangling pin<DIA0>
> > all the way from DIA0 to DIA31.
> I have often seen similar warnings for unused address lines on block
> RAMs for Microblaze or PPC designs. The ROM and RAM are made from the
> same Block RAM primitives, so the same connection lines are there, even
> if not implemented.
> Maybe somebody else will chime in with a more concrete answer though.
aleksa <aleks...@gmail.com> wrote:
>I'm creating a dual-port ROM, both sides are the same: 7-bit address,
>32-bit data.
>Very simple ISE 13.3 project can be downloaded from here:
>http://www.mediafire.com/?xmf55vwdb14qvbf >=EF=BB=BF=EF=BB=BF=EF=BB=BF=EF=BB=BF=EF=BB=BF=EF=BB=BF=EF=BB=BF=EF=BB=BF
>Both Implementing and Generating the bit file gives warning like this
>one:
>PhysDesignRules:812 - Dangling pin <DIA0>
>all the way from DIA0 to DIA31.
No. Open pins should generate a warning. Just tie them to '0'.
-- Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
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