Need some help creating a ring oscillator on a Spartan-3AN
Sam Kerr
into some problems. Namely, it doesn't seem like any oscillation is
occurring. I've hooked up the output signal to LEDs and the serial port,
but neither of these shows any oscillations.
A few things I think might be happening is that the oscillation is so fast
I just can't see it, the oscillation is too fast for the board, it's
getting optimized out during synthesis, or (probably) my Verilog file is
implemented incorrectly.
Can you help me with this? See below for the Verilog modules I'm using.
module ringoscillator(
input wire stop,
output wire out
);
wire connector;
wire w1, w2, w3, w4;
nandgate inputGate(.i1(stop), .i2(connector), .out(w1));
invertergate inv1(.in(w1), .out(w2));
invertergate inv2(.in(w2), .out(w3));
invertergate inv3(.in(w3), .out(w4));
invertergate inv4(.in(w4), .out(connector));
assign out = connector;
endmodule
module nandgate(
input wire i1, i2,
output wire out);
assign out = ~(i1 & i2);
endmodule
module invertergate(
input wire in,
output wire out);
assign out = ~in;
endmodule
Thanks for any help!
Antti
looks xilinx examples if you dont get it working yourself
there are many ways of doing ring oscillators some work too
se sk freq meter ref design includes ring osc
Antti
austin
Most synthesis tools optimize out any unnecessary logic, so the
synthesis tool will look at your code, and remove all but one
inverter.
It will then either not oscillate (not enough delay), or it will
oscillate so fast, you will be unable to see anything on an IO pin.
Read through the synthesis manual, and you will find attributes like
"keep" and "save" which direct the tools to not rip things out (you
really wanted to do something that obvious).
The place and route tools also optimize, so this also may be happening
after synthesis.
Austin
Gabor
I'm not sure this works on wires as well as regs, but try:
(* KEEP = "TRUE" *) wire connector; // This wire should be kept
anyway
(* KEEP = "TRUE" *) wire w1, w2, w3, w4; // Some of these would get
ripped out
Older versions of XST would not keep simple gates. The brute force
method
is to take out and dust off the old libraries guide and instantiate a
LUT
with the appropriate INIT functions for your gates. However I think
that
if you're using a relatively recent version of XST the KEEP attribute
should
do the trick.
Regards,
Gabor
glen herrmannsfeldt
> I'm trying to create a ring oscillator for my FPGA design but I've run
> into some problems. Namely, it doesn't seem like any oscillation is
> occurring. I've hooked up the output signal to LEDs and the serial port,
> but neither of these shows any oscillations.
>
> A few things I think might be happening is that the oscillation is so fast
> I just can't see it, the oscillation is too fast for the board, it's
> getting optimized out during synthesis, or (probably) my Verilog file is
> implemented incorrectly.
If you really mean "see", I am pretty sure it would be too fast
to see on the LED. In the CD4000 series days, we used to make slower
ones with three inverters and an RC delay. (Or maybe with just one.)
If you do keep all three inverters (no optimizing them away), you
should be in the 100's of MHz range. Run through a 30 bit ripple
counter and then you should be able to see it.
-- glen
-jg
> I'm trying to create a ring oscillator for my FPGA design but I've run
> into some problems. Namely, it doesn't seem like any oscillation is
> occurring. I've hooked up the output signal to LEDs and the serial port,
> but neither of these shows any oscillations.
It is 'good practice' when doing ring oscillators, to build them
using
alternate inverter/nand/inverter/nand + final inverter/nand and enable
the nands from your reset.
This ensures it does start correctly, and also helps avoid the
optimize away diseases...
Start with a LOT of elements in your ring, and calculate a delay for
a pair, then revisit your element count.
Not many data sheets have these numbers... I guess they are scared
designers might rely on the numbers.
-jg
Antti
Jim, and others:
4 levels of logic in the "ring" delivers usable clock on most known
FPGA's (assuming it is real 4 levels of logic, that is not optimized
into single lut)
the clock from "4 LL ring oscillator" may be too high to be used as
main system clock, so its good practice to divide with F/F, and use
the divided clock for the rest of the system, or for more margin pre
divide by 4 or 8
the ring clock will be in the frequency range where 1 F/F safely
triggers (this clock may be over 200MHz! depend on family)
Antti
Rob Gaddi
Sam Kerr <stk...@purdue.edu> wrote:
> [snip a ring oscillator]
You know, for one pin, a tinylogic schmitt trigger, an R, and a C (sum
total < $0.10 in quantity), you could have a much easier to work with
clock source.
--
Rob Gaddi, Highland Technology
Email address is currently out of order
Sam Kerr
Function, which specifically calls for a ring oscillator.
-Sam Kerr
Antti
wau, a real PUF designer! :)
and how is it looking? There are plenty of tricks possible, but
i bet its not so easy to make it really reliable
Antti
Krzysztof Kepa
"Sam Kerr" <stk...@purdue.edu> wrote in message
news:alpine.WNT.2.00.0911020916180.1072@stkerr-Vista...
> I'm trying to create a ring oscillator for my FPGA design but I've run
> into some problems. Namely, it doesn't seem like any oscillation is
> occurring. I've hooked up the output signal to LEDs and the serial port,
> but neither of these shows any oscillations.
>
Here you might find useful reference design:
A. Maiti, R. Nagesh, A. Reddy, P. Schaumont, "Physical Unclonable Function
and True Random Number Generator: a Compact and Scalable Implementation,"
19th Great Lakes Symposium on VLSI (GLSVLSI 2009), May 2009.
http://rijndael.ece.vt.edu/schaum/papers/2009glsvlsi.pdf
>
> A few things I think might be happening is that the oscillation is so fast
> I just can't see it, the oscillation is too fast for the board, it's
> getting optimized out during synthesis, or (probably) my Verilog file is
> implemented incorrectly.
>
Constraining inverter's output signals with 'KEEP' attribute will do the
job.
Also, the oscillation frequency for 3 INVs can reach 450-500MHz (when
implemented in V5).
Regards,
Krzysztof
Antti
> "Sam Kerr" <stk...@purdue.edu> wrote in message
>
> news:alpine.WNT.2.00.0911020916180.1072@stkerr-Vista...
>
> > I'm trying to create a ring oscillator for my FPGA design but I've run
> > into some problems. Namely, it doesn't seem like any oscillation is
> > occurring. I've hooked up the output signal to LEDs and the serial port,
> > but neither of these shows any oscillations.
>
> Here you might find useful reference design:
>
> A. Maiti, R. Nagesh, A. Reddy, P. Schaumont, "Physical Unclonable Function
> and True Random Number Generator: a Compact and Scalable Implementation,"
>
>
>
> > A few things I think might be happening is that the oscillation is so fast
> > I just can't see it, the oscillation is too fast for the board, it's
> > getting optimized out during synthesis, or (probably) my Verilog file is
> > implemented incorrectly.
>
> Constraining inverter's output signals with 'KEEP' attribute will do the
> job.
> Also, the oscillation frequency for 3 INVs can reach 450-500MHz (when
> implemented in V5).
>
> Regards,
> Krzysztof
I was able to measure ring oscillator frequency of 975MHz in V4 :)
(but that signal would not travel long in V4 fabric)
Antti
Krzysztof Kepa
"Antti" <antti....@googlemail.com> wrote in message
news:db41b833-0e92-421b...@j4g2000yqe.googlegroups.com...
On Nov 5, 8:41 pm, "Krzysztof Kepa" <nospam_blond...@poczta.fm> wrote:
>> Also, the oscillation frequency for 3 INVs can reach 450-500MHz (when
>> implemented in V5).
>>
>(but that signal would not travel long in V4 fabric)
>
>Antti
Nice, was it on purpose?
I mean I'm just curious whether it required manual routing or simply 'just
happened' ?;)
Regards,
Krzysztof
Antti
> "Antti" <antti.luk...@googlemail.com> wrote in message
on purpose yes :)
just "fabric" speed measurement experiments, and trying out different
primitives to be used as on-chip oscillators
I think i did use RLOCs at least, the 975mhz travels to closest Flip
flop that divides by two, the clock is otherwise
unuseable in V4, ah yes, this was done when i did write my FPGA
Frequency Meter IP cores and JTAG software
well, that software and IP cores still could be used but as it was
depending on LPT based JTAG adapter so it
not much useful now, well at least not with that mode that it was
used, where it was possible to measure
clocks connected to FPGA without having any known reference (JTAG
timing was used as reference)
Antti