vhdl question
CMOS
each input , "obuf_lvcmos33" for each output and "bufg" in some entity
declarations.
In addition please let me know the effect of mappimg clk to clock in
the following entity declaration.
entity test is port (clock : in std_logic )
end clock ;
architecture arch_test of test is
signal clk : std_logic ;
clk <= clock;
end architecture arch_test ;
in the remainder of the definition, only "clk" is used. "clock" is
never used. Why cant we just use "clock".
Symon
news:1128352673.2...@g49g2000cwa.googlegroups.com...
>
> in the remainder of the definition, only "clk" is used. "clock" is
> never used. Why cant we just use "clock".
>
computer. It's important to keep these keys in pristine condition in case
you need to email for coffee or cocoa.
HTH, Syms.
Mike Treseler
> please someone let me know the effects of having "ibuf_lvcmos33" for
> each input , "obuf_lvcmos33" for each output and "bufg" in some entity
> declarations.
These connect the device pins
to the design. If you are using synthesis,
these will be inferred where needed.
> In addition please let me know the effect of mappimg clk to clock in
> the following entity declaration.
No effect for syntheses, other than possible confusion.
An extra delta delay for simulation.
I would just change the port name to clk.
-- Mike Treseler
CMOS
y dont u try a porn group Symon. dont show off ur stupidity a..hole.
CMOS
Simon Peacock
First drop the vowels
clock => clck
then use industry standard TLA's if applicable...
clock => clk
the exception is a reduction that becomes ambiguous
clear as mud I hope
Simon
"Mike Treseler" <mike_t...@comcast.net> wrote in message
news:3qdb1rF...@individual.net...
nospa...@gmail.com
and only the way you use them will determine whether they are clocks
signals or not (or sometimes a combination of both).
clk <= clock has no other effect than changing the signal name and
introducing some delta delays in simulation. The synthesizer will
simplify this code to keep only one signal and will decide whether it
inserts a clock buffer based on other considerations (synthesis
constraints, use of the signal, and so on).
Effects of having ibuf_/obuf_ in VHDL are : 1) specifying @ code-time
which electrical interface your FPGA will have w/ other components on
the board (important to properly identify logic values 0/1 wrt to
electrical voltages) 2) explicitely specifying propagation delays
through the I/O pads of the FPGA in order to take their effect into
account during the VHDL simulation (note however that w/ high-density
FPGA you miss an important contributor to the propagation delay eg the
interconnect capacitance that you'll have to add after a place&route
via a .sdc file).
Eric
Brad Smallridge
I do think it is a good idea on your top level to map the IO pin
to the clk signal in case you want to change that pin or switch
to another clock source. This will save you from having to replace
all the clk signals if you want to move your clock source.
If you have testbeds, too, these will probably
all be written with clk drivers, and so it is sometime a good idea
to write your subordinate modules with clk and map it on
the upper hierarchial modules with such an assignmnet
that you suggest below.
Brad Smallridge
Andy Peters
> please someone let me know the effects of having "ibuf_lvcmos33" for
> each input , "obuf_lvcmos33" for each output and "bufg" in some entity
> declarations.
The ibuf and obufs tell the tools what sort of I/O structure is to be
used. There's some detail on this in the device datasheets.
> In addition please let me know the effect of mappimg clk to clock in
> the following entity declaration.
>
> entity test is port (clock : in std_logic )
>
> end clock ;
>
> architecture arch_test of test is
>
> signal clk : std_logic ;
> clk <= clock;
>
> end architecture arch_test ;
>
> in the remainder of the definition, only "clk" is used. "clock" is
> never used. Why cant we just use "clock".
Perhaps there's a language barrier here, but I have no idea what you're
asking. I suspect that Symon feels the same way.
-a
CMOS
a signal called "clk" declared in the entity. The input "clock" is
mapped to the signal "clk". In all other places only "clk" is used, but
"clock" is never used. What is the difference of doing this from just
using "clock" everywhere and eliminating "clk" altogether?
CMOS
Nicolas Matringe
I'd ask the question the other way round: why not call the input port
'clk'?
Nicolas
Simon Peacock
like clk_100MHz
Simon
"Nicolas Matringe" <nic_...@msn.com> wrote in message
news:1128500245.3...@g44g2000cwa.googlegroups.com...
CMOS
question and not on naming standards of VHDL.
Put it another way, my problem is,
why do we need to map the input to a signal declared in the declaration
and use that signal , rather than just using input. will it result in a
different circuit being synthezised?
CMOS
Mike Treseler
> why do we need to map the input to a signal declared in the declaration
> and use that signal , rather than just using input.
We don't.
Input port IDs can be used directly anywhere
in the architecture on the
right side of an assignment.
my_var := my_inport;
Same for output port IDs used on the
left side of a signal assignment:
my_outport <= my_var;
-- Mike Treseler
Andy Peters
You can, and should, use the port signal "clock" instead of using
assigned signal "clk."
There IS a restriction that applies to using _output_ ports within an
entity's architecture. You can only assign to that signal; you cannot
use it on the right-hand side of an assignment statement. So it's
common to see:
entity foo (a : in std_logic; b : out std_logic); end entity foo;
architecture bar of foo is
signal bletch : std_logic;
begin
bletch <= b; -- not allowed!
end architecture bar;
Is your example from a bit of code someone else wrote and you need to
understand?
-a