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Searching for cost effective PCI express x1 core..

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Morten Leikvoll

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Sep 29, 2009, 3:24:18 AM9/29/09
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..using Altera Stratix3 and TI's XIO1011B PHY.

Altera/PLDA's core is too expensive to use with a yearly fee.
Axcon.dk have a nicer price, but I want to look for even better.

A one off cost with available source code is preferred.


Petter Gustad

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Sep 29, 2009, 4:19:07 AM9/29/09
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"Morten Leikvoll" <mlei...@yahoo.nospam> writes:

Last time I worked with PCIe we rolled our own implementation.
However, we used a verification library from nSys. If you have more
design resources than cash this is a possible way to go.

BTW, the Arria II GX and Stratix IV GX contains PCIe hardmacros,
wouldn't that be a better choice?

Petter
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Morten Leikvoll

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Sep 29, 2009, 6:16:16 AM9/29/09
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"Petter Gustad" <newsma...@gustad.com> wrote in message
news:87zl8e2...@pangea.home.gustad.com...

> "Morten Leikvoll" <mlei...@yahoo.nospam> writes:
>
>> ..using Altera Stratix3 and TI's XIO1011B PHY.
>>
>> Altera/PLDA's core is too expensive to use with a yearly fee.
>> Axcon.dk have a nicer price, but I want to look for even better.
>>
>> A one off cost with available source code is preferred.
>
> Last time I worked with PCIe we rolled our own implementation.
> However, we used a verification library from nSys. If you have more
> design resources than cash this is a possible way to go.
>
> BTW, the Arria II GX and Stratix IV GX contains PCIe hardmacros,
> wouldn't that be a better choice?
>
> Petter

Thanks for the quick reply. The Arrira and Stratix IV are options but will
require some redo of the pcb (the Statix3 was drawn in long time ago, but
our Altera's dealer forgot to mention licensing cost for this core)

Unfortunately we got neither excess of design resources nor cash (hey,
credit crunch still hasn't disappeared ;)


John Adair

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Sep 29, 2009, 5:09:02 PM9/29/09
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We have an Altera variant of our existing X1 PCIe core coming. At the
moment I don't have an exact timescale as we have yet to build the
first target development board that will be used to test this version.
If it's not an immediate need then I will be happy to take this
offline for further discussion on what need and what we can do.

John Adair
Enterpoint Ltd. - Home of Drigmorn3. The Spartan-6 Starter Board.

Charles Gardiner

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Sep 29, 2009, 6:27:19 PM9/29/09
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Hi Morten,

I'd consider the Lattice core to be one of the most cost effective
solutions. It's targetted at their ECP2M / ECP3 FPGA series or hard
wired in their SCM series, Their licensing is very friendly towards
sensitive budgets and most important of all of course, the core works.

If your are just doing a prototype, it has the advantage that you can
test as long as you like without a license. It stops working after 5 to
9 hours (random time out) but can be restarted immediately.

Cost is once off (as far as I know, somewhere below ᅵ 1K, but better ask
a Lattice disti for real figures). You get 'obfuscated verilog' which
cannot really be modified by the user. Their configure tool should be
good enough though for setting it up the way you need it.


pcie-rat

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Nov 4, 2009, 5:25:03 AM11/4/09
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Morten,

Whatever solution you go with - my advice is this:

* Get readable commented source code - or get a good option to buy it
at a decent cost. It pays in the end.

* When thinking about price, take your own cost into consideration.
One engineering day in the Nordic region cost about EUR 5-600 all
included (yes, more than just salary). So if you are trying to save
say EUR 4000 (which incidentally is about 50% of the solution we
have :-), you have about 7 days in total to do so. This needs to
include everything. And that is just breaking even. If your company
usually have you do something that is more valuable than the cost of
having you hanging around :-) Which I hope they do :-) They would want
you to generate more savings than the time you spend. So better budget
at most about 3-4 days to save the EUR 4000 :-)

// Rolf

--
Axcon - The FPGA Power House
www.axcon.dk | PCIe core: http://en.axcon.dk/pcie-core/
FPGA Training: www.axcon.dk/training | Also don't miss:
Signal Integrity w/ Lee Ritchey: www.axcon.dk/lee (Dec 1-3/09)

Morten Leikvoll

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Nov 9, 2009, 4:50:47 AM11/9/09
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"pcie-rat" <r...@axcon.dk> wrote in message
news:320bb306-e1b8-41f0...@m16g2000yqc.googlegroups.com...

> Morten,
>
> Whatever solution you go with - my advice is this:
>
> * Get readable commented source code - or get a good option to buy it
> at a decent cost. It pays in the end.

I agree that is a plus. Spending time on support is not creating added
value. I'd rather spend the time on correcting/improving the problems
myself.

> * When thinking about price, take your own cost into consideration.
> One engineering day in the Nordic region cost about EUR 5-600 all
> included (yes, more than just salary). So if you are trying to save
> say EUR 4000 (which incidentally is about 50% of the solution we
> have :-), you have about 7 days in total to do so. This needs to
> include everything. And that is just breaking even. If your company
> usually have you do something that is more valuable than the cost of
> having you hanging around :-) Which I hope they do :-) They would want
> you to generate more savings than the time you spend. So better budget
> at most about 3-4 days to save the EUR 4000 :-)

I don't fully agree with that although I can see it from your perspective
(especially if the market is small). Competition is to the benefit of the
buyer. It will be like saying it is ok to pay $100 for a bread, cause the
process of doing all from scratch yourself is gonna cost much much more. For
low quantity volumes and a price like that can kill the project. To continue
my comparison, it would prevent any cafe's to open, cause the price of bread
would not make it profitable.

:)


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