Google Groups no longer supports new Usenet posts or subscriptions. Historical content remains viewable.
Dismiss

ISE 9.2 - how do I extract component/slice placements for locking down a design?

2 views
Skip to first unread message

Fred

unread,
May 9, 2008, 12:23:33 PM5/9/08
to
Is there any NGD reader which can extract placement information?

I know I can use FPGA editor and go through all the primitives, one by
one, but this would be a mamoth task! Any ideas?

Kevin Neilson

unread,
May 9, 2008, 1:14:43 PM5/9/08
to

Are you trying to floorplan or trying to figure out how PAR performed
placement? If the former, PlanAhead is a very nice tool for
floorplanning. -Kevin

SoyAnarchisto

unread,
May 9, 2008, 5:42:35 PM5/9/08
to
Fred,

ngd does not have placement information, I think you are referring to
ncd. Beginning w/ ISE 10.1 PlanAhead is shipped with all versions of
ISE, including the webpack (free) version. Prior to that PlanAhead
was a separate optional tool, but evaluation licenses are readily
available for the asking:

http://www.xilinx.com/ise/optional_prod/planahead.htm

PlanAhead is a fairly straightforward tool to use. At a high level,
to do what you are asking:

1) download and install planAhead
2) create a project by importing an edif/ngc netlist and optionally
ucf constraints (and pick a target device if ngc).
3) File->Import Placement and browse to your placed and/or routed ncd
file

This will import placement from an ncd file and convert them to LOC
and BEL constraints.

At this point you have tons of options, depending on what you are
trying to accomplish. You can go to File->Export Floorplan to write
out all these loc/bels into a ucf file, but a huge file of locs is of
limited use, for floorplanning, timing closure, ip reuse flows.

Take a look at the PlanAhead tutorial and methodology guides, as a
starting point. More questions will doubtlessly follow...

'Greg

On May 9, 11:14 am, Kevin Neilson

Fred

unread,
May 10, 2008, 5:35:31 AM5/10/08
to
Hi Greg, Kevin,

Many thanks for your reply. In essence I want to take a completed design,
with critical timing constraints, and import it as an IP_Core into EDK where
the added logic has very lax timing constraints.

I would like to take the component placement for the fitted critical part
and lock these down. I want to use this new UCF file with all the placement
information in EDK with a hope that timing may be achieved which it doesn't
at present.

I will certainly look at Floorplanner to see how this can help.

Many thanks again.

Fred


"SoyAnarchisto" <greg.d...@gmail.com> wrote in message
news:35098c3c-3117-4083...@a23g2000hsc.googlegroups.com...

0 new messages