New Virtex4 Project, CoreGen
Brandon
on some possible target platforms. I've never created a project from
scratch, I've only used vendor supplied projects to implement my
designs, so I'm lost .
Here's my entity w/ instantiation:
<SNIP>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
entity coreest is
port (
clk_in: in std_logic;
reset: in std_logic;
din: in std_logic_vector(15 downto 0);
dout: out std_logic_vector(15 downto 0)
);
end coreest;
architecture str_ar of coreest is
component BUFG is
port (
I : in std_logic;
O : out std_logic
);
end component;
component macfir
port (
CLK: IN std_logic;
RESET: IN std_logic;
ND: IN std_logic;
RDY: OUT std_logic;
RFD: OUT std_logic;
DIN: IN std_logic_VECTOR(15 downto 0);
DOUT: OUT std_logic_VECTOR(37 downto 0));
end component;
signal clk: std_logic;
signal macfir_nd: std_logic;
signal macfir_din: std_logic_vector(15 DOWNTO 0);
signal macfir_rdy: std_logic;
signal macfir_rfd: std_logic;
signal macfir_dout: std_logic_vector(37 DOWNTO 0);
begin
clk_in_bufg_inst : BUFG
port map(
I => clk_in,
O => clk
);
macfir_inst : macfir
port map (
CLK => clk,
RESET => reset,
ND => macfir_nd,
DIN => macfir_din,
RDY => macfir_rdy,
RFD => macfir_rfd,
DOUT => macfir_dout
);
macfir_nd <= '1';
macfir_din <= din;
dout <= macfir_dout(macfir_dout'high downto
macfir_dout'high-dout'length+1);
end str_ar;
</SNIP>
The 'macfir_inst' instance is a CoreGen entity, 'macfir (macfir.xco)'
generated from the Xilinx FIR core. I configured it correctly and
everything seems okay, except synthesis, which is not even recognizing
the global clock net:
<SNIP>
=========================================================================
* HDL Compilation
*
=========================================================================
WARNING:HDLParsers:3498 - No primary, secondary unit in the file
"C:/Work/HDL/CoreEst/macfir.vhd. Ignore this file from project file
"C:/Work/HDL/CoreEst/coreest_vhdl.prj".
Compiling vhdl file "C:/Work/HDL/CoreEst/coreest.vhd" in Library work.
Entity <coreest> compiled.
Entity <coreest> (Architecture <str_ar>) compiled.
=========================================================================
* HDL Analysis
*
=========================================================================
Analyzing Entity <coreest> (Architecture <str_ar>).
WARNING:Xst:766 - "C:/Work/HDL/CoreEst/coreest.vhd" line 67: Generating
a Black Box for component <BUFG>.
Entity <coreest> analyzed. Unit <coreest> generated.
Analyzing module <macfir>.
Module <macfir> is correct for synthesis.
WARNING:Xst:37 - Unknown property "black_box".
=========================================================================
* HDL Synthesis
*
=========================================================================
Synthesizing Unit <macfir>.
Related source file is "macfir.v".
WARNING:Xst:647 - Input <CLK> is never used.
WARNING:Xst:647 - Input <DIN> is never used.
WARNING:Xst:647 - Input <RESET> is never used.
WARNING:Xst:647 - Input <ND> is never used.
WARNING:Xst:1305 - Output <RFD> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <RDY> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <DOUT> is never assigned. Tied to value
00000000000000000000000000000000000000.
Unit <macfir> synthesized.
Synthesizing Unit <coreest>.
Related source file is "C:/Work/HDL/CoreEst/coreest.vhd".
WARNING:Xst:646 - Signal <macfir_dout<21:0>> is assigned but never
used.
WARNING:Xst:646 - Signal <macfir_rfd> is assigned but never used.
WARNING:Xst:646 - Signal <macfir_rdy> is assigned but never used.
Unit <coreest> synthesized.
=========================================================================
HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Advanced HDL Synthesis
*
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Low Level Synthesis
*
=========================================================================
Loading device for application Rf_Device from file '4vsx55.nph' in
environment C:\Xilinx.
Optimizing unit <coreest> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block coreest, actual ratio
is 0.
=========================================================================
* Final Report
*
=========================================================================
Final Results
RTL Top Level Output File Name : coreest.ngr
Top Level Output File Name : coreest
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 34
Cell Usage :
# BELS : 1
# GND : 1
# IO Buffers : 16
# OBUF : 16
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 4vsx55ff1148-12
Number of bonded IOBs: 16 out of 640 2%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
---------------
Speed Grade: -12
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
</SNIP>