XOR?
Short non-descriptive posts get you short non-descriptive answers. : )
Try the data sheet for the Analog Devices phase comparator. Google for it!
Google HC4046
Homework?
Cheers
PeteS
Heh heh
The MC4044 is my favourite phase detector whether in a MC4044 package or
modelled in an FPGA.
Cheers
PeteS
Vasiliy
Vasiliy,
It works just fine, although the timing tools will give you grief
over the combinatorial feedback loop, and simulators may choke on it.
You might double check that your PU/PD are pumping in the right
direction, and that your external analog filter is correct.
An altermative implementation uses a pair of FFs, one clocked high by
your feedback clock, one clocked high by the reference clock, and both
asynchronously reset when both are high. PU and PD are decoded when one
or the other FF is high. Slightly more simulator friendly.
Just John
The HC4046 uses this topology.
The OP could also drop in a 4046, and get the system working, then
transfer
pieces into the FPGA. That's a good way to confirm other parts are OK,
plus you have a working reference for things like phase noise in the
phase detector/charge pump sections.
FPGA pumps will use the FPGA rails, so for lower noise (if that
matters)
you can drive analog switches from the FPGA
-jg
Perhaps what you really want is a frequency detector?
A phase detector is only useful when the two signals being compared are
very, very close in frequency, such that a phase detector obtains a
useful output.
Please examine "frequency-phase detectors." That may provide you with
some guidance,
Austin
Vasiliy
Here's a repost from 2003! BTW, since then I now think the equivalent
circuit made from two FFs is much better.
Hi,
A small note of caution when using Peter's XAPP028 in Virtex II. As
well as constraining the logic to the CLBs shown in the app note, make
sure you specify a MAXSKEW attribute on the reference signal and
feedback signal to the circuit. I use 100ps. Without this the circuit
can occasionally malfunction depending on the place and route. (These
are the signals called 'from VCO divided by N' and 'from reference
frequency'.)
There was no problem when this circuit was used on older FPGAs
where the routing to the F and G lookup tables in a single CLB was
guaranteed to have low skew. In Virtex II this is no longer the case
and a single signal that goes to both the F and G inputs of a CLB can
have significant skew if not constrained. This can cause the circuit
of XAPP28 to misbehave.
Of course it's not your fault Peter that those guys changed the
routing from the original 3000 (I guess) design! Thanks for a good APP
note I've used many times, maybe it needs a small update!
HTH, Syms.
p.s. I'm not sure which Xilinx families need the MAXSKEW, I use it
always because it can't hurt. Also, make sure the signals don't
connect anywhere else, or the MAXSKEW will fail. Replicate them if
necessary.