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Phasse Detector

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axalay

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Jan 19, 2007, 3:49:10 AM1/19/07
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Share please the circuit of the phase detector (I do not want to invent
a bicycle). Any of the circuits laid out in an Internet does not work.

motty

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Jan 19, 2007, 10:09:34 AM1/19/07
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axalay wrote:
> Share please the circuit of the phase detector (I do not want to invent
> a bicycle). Any of the circuits laid out in an Internet does not work.

XOR?

Short non-descriptive posts get you short non-descriptive answers. : )

Tim

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Jan 19, 2007, 10:29:19 AM1/19/07
to
> axalay wrote:
>> Share please the circuit of the phase detector (I do not want to invent
>> a bicycle). Any of the circuits laid out in an Internet does not work.
>

Try the data sheet for the Analog Devices phase comparator. Google for it!


-jg

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Jan 19, 2007, 3:10:49 PM1/19/07
to
axalay wrote:
> Share please the circuit of the phase detector (I do not want to invent
> a bicycle). Any of the circuits laid out in an Internet does not work.

Google HC4046

PeteS

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Jan 19, 2007, 4:58:34 PM1/19/07
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axalay wrote:
> Share please the circuit of the phase detector (I do not want to invent
> a bicycle). Any of the circuits laid out in an Internet does not work.
>

Homework?

Cheers

PeteS

Peter Alfke

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Jan 19, 2007, 5:25:45 PM1/19/07
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The classical 30+-year old phase/frequency comparator is the Motorola
MC4044.
(I copied its structure into my Xilinx app note XAPP028)
Just google both these circuits...
Peter Alfke

PeteS

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Jan 19, 2007, 7:00:12 PM1/19/07
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Heh heh

The MC4044 is my favourite phase detector whether in a MC4044 package or
modelled in an FPGA.

Cheers

PeteS

axalay

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Jan 20, 2007, 4:16:19 AM1/20/07
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XOR - is not detrct + or - phase shift. And I not use external phase
detect chips. I whant do it in FPGA. And structure of phase detector
from XAPP028 is not work!

Vasiliy

JustJohn

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Jan 20, 2007, 10:35:12 AM1/20/07
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Vasiliy,
It works just fine, although the timing tools will give you grief
over the combinatorial feedback loop, and simulators may choke on it.
You might double check that your PU/PD are pumping in the right
direction, and that your external analog filter is correct.

An altermative implementation uses a pair of FFs, one clocked high by
your feedback clock, one clocked high by the reference clock, and both
asynchronously reset when both are high. PU and PD are decoded when one
or the other FF is high. Slightly more simulator friendly.

Just John

-jg

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Jan 20, 2007, 3:50:45 PM1/20/07
to

The HC4046 uses this topology.
The OP could also drop in a 4046, and get the system working, then
transfer
pieces into the FPGA. That's a good way to confirm other parts are OK,
plus you have a working reference for things like phase noise in the
phase detector/charge pump sections.
FPGA pumps will use the FPGA rails, so for lower noise (if that
matters)
you can drive analog switches from the FPGA

-jg

David R Brooks

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Jan 20, 2007, 5:01:48 PM1/20/07
to
An XOR most certainly can work as a phase detector, *provided* the input
frequencies are reasonably close. What it cannot do it give a valid
output when the inputs differ significantly in frequency. (This may make
it unsuitable for your use.)
To see how it works, imagine two inputs of almost equal frequency, so
the phase shifts slowly. When they are in phase, the XOR gives a zero
output: when they are exactly out of phase it gives '1'. Used in a PLL,
it will seek to give a 50-50 square-wave output, corresponding to a 90
degree phase difference. Your loop filter then integrates this to a
voltage at 50% of Vdd.
In fact (subject to the overall loop dynamics), XOR will work with more
difference between the input frequencies than you might expect: it just
won't work over as wide a range as the flipflop designs.

Austin

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Jan 20, 2007, 8:20:20 PM1/20/07
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Vasily

Perhaps what you really want is a frequency detector?

A phase detector is only useful when the two signals being compared are
very, very close in frequency, such that a phase detector obtains a
useful output.

Please examine "frequency-phase detectors." That may provide you with
some guidance,

Austin

axalay

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Jan 22, 2007, 2:25:44 AM1/22/07
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Thank for all.

Vasiliy

Symon

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Jan 22, 2007, 9:14:43 AM1/22/07
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"Peter Alfke" <pe...@xilinx.com> wrote in message
news:1169245545.1...@l53g2000cwa.googlegroups.com...

> The classical 30+-year old phase/frequency comparator is the Motorola
> MC4044.
> (I copied its structure into my Xilinx app note XAPP028)
> Just google both these circuits...
> Peter Alfke
>

Here's a repost from 2003! BTW, since then I now think the equivalent
circuit made from two FFs is much better.

Hi,
A small note of caution when using Peter's XAPP028 in Virtex II. As
well as constraining the logic to the CLBs shown in the app note, make
sure you specify a MAXSKEW attribute on the reference signal and
feedback signal to the circuit. I use 100ps. Without this the circuit
can occasionally malfunction depending on the place and route. (These
are the signals called 'from VCO divided by N' and 'from reference
frequency'.)
There was no problem when this circuit was used on older FPGAs
where the routing to the F and G lookup tables in a single CLB was
guaranteed to have low skew. In Virtex II this is no longer the case
and a single signal that goes to both the F and G inputs of a CLB can
have significant skew if not constrained. This can cause the circuit
of XAPP28 to misbehave.
Of course it's not your fault Peter that those guys changed the
routing from the original 3000 (I guess) design! Thanks for a good APP
note I've used many times, maybe it needs a small update!
HTH, Syms.
p.s. I'm not sure which Xilinx families need the MAXSKEW, I use it
always because it can't hurt. Also, make sure the signals don't
connect anywhere else, or the MAXSKEW will fail. Replicate them if
necessary.


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